Search

Dang T. Ton

Examiner (ID: 7746, Phone: (571)272-3171 , Office: P/2476 )

Most Active Art Unit
2476
Art Unit(s)
2476, 2661, OPT, 2603, 2666, 2616, 2899, 2732, 2475
Total Applications
2064
Issued Applications
1715
Pending Applications
214
Abandoned Applications
162

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12314532 [patent_doc_number] => 09941230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Electrical connecting structure between a substrate and a semiconductor chip [patent_app_type] => utility [patent_app_number] => 14/985009 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/985009
Electrical connecting structure between a substrate and a semiconductor chip Dec 29, 2015 Issued
Array ( [id] => 11050797 [patent_doc_number] => 20160247756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'CAPPING POLY CHANNEL PILLARS IN STACKED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/979304 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11514 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979304
Capping poly channel pillars in stacked circuits Dec 21, 2015 Issued
Array ( [id] => 11265801 [patent_doc_number] => 09490103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Separation of chips on a substrate' [patent_app_type] => utility [patent_app_number] => 14/977625 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4544 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977625 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977625
Separation of chips on a substrate Dec 20, 2015 Issued
Array ( [id] => 10758512 [patent_doc_number] => 20160104664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A PLURALITY OF CIRCUITS ARRANGED ON A SIDE OF A SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 14/972369 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14604 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972369 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972369
Semiconductor device having a plurality of circuits arranged on a side of a semiconductor chip Dec 16, 2015 Issued
Array ( [id] => 11431981 [patent_doc_number] => 09570305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Self-aligned double patterning' [patent_app_type] => utility [patent_app_number] => 14/973373 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973373 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973373
Self-aligned double patterning Dec 16, 2015 Issued
Array ( [id] => 12087057 [patent_doc_number] => 09840776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Multi-station plasma reactor with RF balancing' [patent_app_type] => utility [patent_app_number] => 14/970337 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970337
Multi-station plasma reactor with RF balancing Dec 14, 2015 Issued
Array ( [id] => 10738326 [patent_doc_number] => 20160084477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'NOVEL ILLUMINATION DEVICES' [patent_app_type] => utility [patent_app_number] => 14/963713 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4850 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963713 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963713
NOVEL ILLUMINATION DEVICES Dec 8, 2015 Abandoned
Array ( [id] => 10740759 [patent_doc_number] => 20160086910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/964096 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964096 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964096
Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same Dec 8, 2015 Issued
Array ( [id] => 10753276 [patent_doc_number] => 20160099428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'Flexible Organic Light-Emitting Display Device and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 14/958852 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9312 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958852
Flexible organic light-emitting display device and method for manufacturing the same Dec 2, 2015 Issued
Array ( [id] => 13629777 [patent_doc_number] => 20180366441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => DIE STACK WITH CASCADE AND VERTICAL CONNECTIONS [patent_app_type] => utility [patent_app_number] => 15/780506 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15780506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/780506
Die stack with cascade and vertical connections Dec 1, 2015 Issued
Array ( [id] => 10826039 [patent_doc_number] => 20160172207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'PELLICLE MEMBRANE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/955455 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955455 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/955455
PELLICLE MEMBRANE AND METHOD OF MANUFACTURING THE SAME Nov 30, 2015 Abandoned
Array ( [id] => 11432125 [patent_doc_number] => 09570450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Hybrid logic and SRAM contacts' [patent_app_type] => utility [patent_app_number] => 14/945497 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7784 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945497
Hybrid logic and SRAM contacts Nov 18, 2015 Issued
Array ( [id] => 13214643 [patent_doc_number] => 10121697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Semiconductor constructions; and methods for providing electrically conductive material within openings [patent_app_type] => utility [patent_app_number] => 14/930524 [patent_app_country] => US [patent_app_date] => 2015-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3785 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930524 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930524
Semiconductor constructions; and methods for providing electrically conductive material within openings Nov 1, 2015 Issued
Array ( [id] => 11608059 [patent_doc_number] => 20170125362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'Multi-Die Package Having Different Types of Semiconductor Dies Attached to the Same Thermally Conductive Flange' [patent_app_type] => utility [patent_app_number] => 14/928812 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5052 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/928812
Multi-die package having different types of semiconductor dies attached to the same thermally conductive flange Oct 29, 2015 Issued
Array ( [id] => 10681513 [patent_doc_number] => 20160027658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'Lithography using Multilayer Spacer for Reduced Spacer Footing' [patent_app_type] => utility [patent_app_number] => 14/878798 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878798
Lithography using multilayer spacer for reduced spacer footing Oct 7, 2015 Issued
Array ( [id] => 14801547 [patent_doc_number] => 10403785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Wavelength converting material deposition methods and associated articles [patent_app_type] => utility [patent_app_number] => 14/867952 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 8946 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867952 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/867952
Wavelength converting material deposition methods and associated articles Sep 27, 2015 Issued
Array ( [id] => 11214819 [patent_doc_number] => 09443860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Semiconductor device having E-fuse and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/862908 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 12259 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862908 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862908
Semiconductor device having E-fuse and method for fabricating the same Sep 22, 2015 Issued
Array ( [id] => 11180755 [patent_doc_number] => 09412752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Reference line and bit line structure for 3D memory' [patent_app_type] => utility [patent_app_number] => 14/861377 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 12034 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14861377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/861377
Reference line and bit line structure for 3D memory Sep 21, 2015 Issued
Array ( [id] => 11802396 [patent_doc_number] => 09543299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-10 [patent_title] => 'P-N bimodal conduction resurf LDMOS' [patent_app_type] => utility [patent_app_number] => 14/861912 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5386 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14861912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/861912
P-N bimodal conduction resurf LDMOS Sep 21, 2015 Issued
Array ( [id] => 11300586 [patent_doc_number] => 09508597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-29 [patent_title] => '3D fin tunneling field effect transistor' [patent_app_type] => utility [patent_app_number] => 14/858154 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5752 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858154 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/858154
3D fin tunneling field effect transistor Sep 17, 2015 Issued
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