Search

Daniel A. Hess

Examiner (ID: 9166, Phone: (571)272-2392 , Office: P/2876 )

Most Active Art Unit
2876
Art Unit(s)
2876
Total Applications
2022
Issued Applications
1569
Pending Applications
141
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9620800 [patent_doc_number] => 08790972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-29 [patent_title] => 'Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment' [patent_app_type] => utility [patent_app_number] => 12/859644 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6223 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12859644 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859644
Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment Aug 18, 2010 Issued
Array ( [id] => 7784309 [patent_doc_number] => 20120045865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'Doped Graphene Films With Reduced Sheet Resistance' [patent_app_type] => utility [patent_app_number] => 12/859426 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045865.pdf [firstpage_image] =>[orig_patent_app_number] => 12859426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859426
Doped graphene films with reduced sheet resistance Aug 18, 2010 Issued
Array ( [id] => 7561346 [patent_doc_number] => 20110275179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'PROTECTIVE TAPE JOINING METHOD AND PROTECTIVE TAPE USED THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/144581 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6455 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20110275179.pdf [firstpage_image] =>[orig_patent_app_number] => 13144581 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144581
PROTECTIVE TAPE JOINING METHOD AND PROTECTIVE TAPE USED THEREFOR Jul 25, 2010 Abandoned
Array ( [id] => 8834464 [patent_doc_number] => 08450220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Substrate processing apparatus , method of manufacturing semiconductor device, and method of manufacturing substrate' [patent_app_type] => utility [patent_app_number] => 12/825005 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 16660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12825005 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825005
Substrate processing apparatus , method of manufacturing semiconductor device, and method of manufacturing substrate Jun 27, 2010 Issued
Array ( [id] => 6348641 [patent_doc_number] => 20100330802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/824381 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4255 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330802.pdf [firstpage_image] =>[orig_patent_app_number] => 12824381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824381
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Jun 27, 2010 Abandoned
Array ( [id] => 6096668 [patent_doc_number] => 20110003482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/825012 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19882 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20110003482.pdf [firstpage_image] =>[orig_patent_app_number] => 12825012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825012
Method of manufacturing semiconductor device and substrate processing system Jun 27, 2010 Issued
Array ( [id] => 6348621 [patent_doc_number] => 20100330799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/823536 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8239 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330799.pdf [firstpage_image] =>[orig_patent_app_number] => 12823536 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823536
SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME Jun 24, 2010 Abandoned
Array ( [id] => 6213027 [patent_doc_number] => 20110136327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'HIGH MOBILITY MONOLITHIC P-I-N DIODES' [patent_app_type] => utility [patent_app_number] => 12/824032 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5898 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20110136327.pdf [firstpage_image] =>[orig_patent_app_number] => 12824032 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824032
High mobility monolithic p-i-n diodes Jun 24, 2010 Issued
Array ( [id] => 6376024 [patent_doc_number] => 20100301471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'LOW-RESISTANCE ELECTRODE DESIGN' [patent_app_type] => utility [patent_app_number] => 12/791259 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301471.pdf [firstpage_image] =>[orig_patent_app_number] => 12791259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791259
Low-resistance electrode design May 31, 2010 Issued
Array ( [id] => 7577307 [patent_doc_number] => 20110291189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR' [patent_app_type] => utility [patent_app_number] => 12/789699 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3231 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291189.pdf [firstpage_image] =>[orig_patent_app_number] => 12789699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789699
Thin channel device and fabrication method with a reverse embedded stressor May 27, 2010 Issued
Array ( [id] => 8071787 [patent_doc_number] => 20110241127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Well implant through dummy gate oxide in gate-last process' [patent_app_type] => utility [patent_app_number] => 12/789780 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6544 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241127.pdf [firstpage_image] =>[orig_patent_app_number] => 12789780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789780
Well implant through dummy gate oxide in gate-last process May 27, 2010 Issued
Array ( [id] => 6177582 [patent_doc_number] => 20110121350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/790640 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121350.pdf [firstpage_image] =>[orig_patent_app_number] => 12790640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/790640
Organic light-emitting display apparatus and method of manufacturing the same May 27, 2010 Issued
Array ( [id] => 7577320 [patent_doc_number] => 20110291202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE' [patent_app_type] => utility [patent_app_number] => 12/789839 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2824 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291202.pdf [firstpage_image] =>[orig_patent_app_number] => 12789839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789839
Device and method of reducing junction leakage May 27, 2010 Issued
Array ( [id] => 7577183 [patent_doc_number] => 20110291065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/787070 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4822 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291065.pdf [firstpage_image] =>[orig_patent_app_number] => 12787070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787070
Phase change memory cell structures and methods May 24, 2010 Issued
Array ( [id] => 7527292 [patent_doc_number] => 08043884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'Methods of seamless gap filling' [patent_app_type] => utility [patent_app_number] => 12/786249 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3539 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/043/08043884.pdf [firstpage_image] =>[orig_patent_app_number] => 12786249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786249
Methods of seamless gap filling May 23, 2010 Issued
Array ( [id] => 6376180 [patent_doc_number] => 20100301489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS FORMED BASED ON A SACRIFICIAL MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/786019 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10069 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301489.pdf [firstpage_image] =>[orig_patent_app_number] => 12786019 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786019
Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material May 23, 2010 Issued
Array ( [id] => 7550620 [patent_doc_number] => 08062952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors' [patent_app_type] => utility [patent_app_number] => 12/784819 [patent_app_country] => US [patent_app_date] => 2010-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 10233 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/062/08062952.pdf [firstpage_image] =>[orig_patent_app_number] => 12784819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/784819
Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors May 20, 2010 Issued
Array ( [id] => 6255909 [patent_doc_number] => 20100295038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'METHOD OF MANUFACTURING FIELD-EFFECT TRANSISTOR, FIELD-EFFECT TRANSISTOR, AND METHOD OF MANUFACTURING DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/782710 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295038.pdf [firstpage_image] =>[orig_patent_app_number] => 12782710 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782710
Method of manufacturing field-effect transistor, field-effect transistor, and method of manufacturing display device May 18, 2010 Issued
Array ( [id] => 10165301 [patent_doc_number] => 09196530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-24 [patent_title] => 'Forming self-aligned conductive lines for resistive random access memories' [patent_app_type] => utility [patent_app_number] => 12/782809 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1922 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12782809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782809
Forming self-aligned conductive lines for resistive random access memories May 18, 2010 Issued
Array ( [id] => 7490396 [patent_doc_number] => 08030157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Liner protection in deep trench etching' [patent_app_type] => utility [patent_app_number] => 12/782050 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030157.pdf [firstpage_image] =>[orig_patent_app_number] => 12782050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782050
Liner protection in deep trench etching May 17, 2010 Issued
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