Search

Daniel A. Hess

Examiner (ID: 9166, Phone: (571)272-2392 , Office: P/2876 )

Most Active Art Unit
2876
Art Unit(s)
2876
Total Applications
2022
Issued Applications
1569
Pending Applications
141
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4533449 [patent_doc_number] => 07871934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Method for an integrated circuit contact' [patent_app_type] => utility [patent_app_number] => 11/841906 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2647 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/871/07871934.pdf [firstpage_image] =>[orig_patent_app_number] => 11841906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841906
Method for an integrated circuit contact Aug 19, 2007 Issued
Array ( [id] => 341534 [patent_doc_number] => 07501292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Method for managing UV irradiation for curing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/780021 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7101 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501292.pdf [firstpage_image] =>[orig_patent_app_number] => 11780021 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780021
Method for managing UV irradiation for curing semiconductor substrate Jul 18, 2007 Issued
Array ( [id] => 185210 [patent_doc_number] => 07645663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method of producing non volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/779810 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5862 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/645/07645663.pdf [firstpage_image] =>[orig_patent_app_number] => 11779810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779810
Method of producing non volatile memory device Jul 17, 2007 Issued
Array ( [id] => 292254 [patent_doc_number] => 07544544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Low capacitance two-terminal barrier controlled TVS diodes' [patent_app_type] => utility [patent_app_number] => 11/879424 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 6950 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/544/07544544.pdf [firstpage_image] =>[orig_patent_app_number] => 11879424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/879424
Low capacitance two-terminal barrier controlled TVS diodes Jul 16, 2007 Issued
Array ( [id] => 210369 [patent_doc_number] => 07625768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Transfer molding apparatus and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/771057 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6651 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/625/07625768.pdf [firstpage_image] =>[orig_patent_app_number] => 11771057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771057
Transfer molding apparatus and method for manufacturing semiconductor device Jun 28, 2007 Issued
Array ( [id] => 4708045 [patent_doc_number] => 20080296571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'MULTI-PROJECT WAFER AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 11/755461 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2680 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296571.pdf [firstpage_image] =>[orig_patent_app_number] => 11755461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/755461
Multi-project wafer and method of making same May 29, 2007 Issued
Array ( [id] => 884296 [patent_doc_number] => 07351597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Fabrication method of semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/750371 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 12813 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/351/07351597.pdf [firstpage_image] =>[orig_patent_app_number] => 11750371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/750371
Fabrication method of semiconductor integrated circuit device May 17, 2007 Issued
Array ( [id] => 93142 [patent_doc_number] => 07732910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Lead frame including suspending leads having trenches formed therein' [patent_app_type] => utility [patent_app_number] => 11/730682 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6495 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732910.pdf [firstpage_image] =>[orig_patent_app_number] => 11730682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730682
Lead frame including suspending leads having trenches formed therein Apr 2, 2007 Issued
Array ( [id] => 5098751 [patent_doc_number] => 20070182011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Method for forming a redistribution layer in a wafer structure' [patent_app_type] => utility [patent_app_number] => 11/730654 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2541 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20070182011.pdf [firstpage_image] =>[orig_patent_app_number] => 11730654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730654
Method for forming a redistribution layer in a wafer structure Apr 2, 2007 Issued
Array ( [id] => 318623 [patent_doc_number] => 07521332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Resistance-based etch depth determination for SGT technology' [patent_app_type] => utility [patent_app_number] => 11/690581 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2393 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521332.pdf [firstpage_image] =>[orig_patent_app_number] => 11690581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690581
Resistance-based etch depth determination for SGT technology Mar 22, 2007 Issued
Array ( [id] => 162405 [patent_doc_number] => 07670964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Apparatus and methods of forming a gas cluster ion beam using a low-pressure source' [patent_app_type] => utility [patent_app_number] => 11/689572 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5525 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670964.pdf [firstpage_image] =>[orig_patent_app_number] => 11689572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689572
Apparatus and methods of forming a gas cluster ion beam using a low-pressure source Mar 21, 2007 Issued
Array ( [id] => 159143 [patent_doc_number] => 07674648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Extended dynamic range using variable sensitivity pixels' [patent_app_type] => utility [patent_app_number] => 11/689072 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2083 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/674/07674648.pdf [firstpage_image] =>[orig_patent_app_number] => 11689072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689072
Extended dynamic range using variable sensitivity pixels Mar 20, 2007 Issued
Array ( [id] => 5063200 [patent_doc_number] => 20070224840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Method of Plasma Processing with In-Situ Monitoring and Process Parameter Tuning' [patent_app_type] => utility [patent_app_number] => 11/687822 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3030 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20070224840.pdf [firstpage_image] =>[orig_patent_app_number] => 11687822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687822
Method of Plasma Processing with In-Situ Monitoring and Process Parameter Tuning Mar 18, 2007 Abandoned
Array ( [id] => 299743 [patent_doc_number] => 07537942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Counting circuit for controlling an off-chip driver and method of changing and output current value of the off-chip driver using the same' [patent_app_type] => utility [patent_app_number] => 11/685870 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3677 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/537/07537942.pdf [firstpage_image] =>[orig_patent_app_number] => 11685870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685870
Counting circuit for controlling an off-chip driver and method of changing and output current value of the off-chip driver using the same Mar 13, 2007 Issued
Array ( [id] => 5157548 [patent_doc_number] => 20070170592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Apparatus for solder crack deflection' [patent_app_type] => utility [patent_app_number] => 11/717902 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170592.pdf [firstpage_image] =>[orig_patent_app_number] => 11717902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717902
Apparatus for solder crack deflection Mar 12, 2007 Issued
Array ( [id] => 4974345 [patent_doc_number] => 20070215574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'PREDICTION METHOD AND APPARATUS FOR SUBSTRATE PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/684298 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14902 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20070215574.pdf [firstpage_image] =>[orig_patent_app_number] => 11684298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684298
Prediction method and apparatus for substrate processing apparatus Mar 8, 2007 Issued
Array ( [id] => 92004 [patent_doc_number] => 07732314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-08 [patent_title] => 'Method for depositing a diffusion barrier for copper interconnect applications' [patent_app_type] => utility [patent_app_number] => 11/714465 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732314.pdf [firstpage_image] =>[orig_patent_app_number] => 11714465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714465
Method for depositing a diffusion barrier for copper interconnect applications Mar 4, 2007 Issued
Array ( [id] => 4872657 [patent_doc_number] => 20080199391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Method for circuits inspection and the method of the same' [patent_app_type] => utility [patent_app_number] => 11/707920 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1394 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20080199391.pdf [firstpage_image] =>[orig_patent_app_number] => 11707920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707920
Method for circuits inspection and method of the same Feb 19, 2007 Issued
Array ( [id] => 830833 [patent_doc_number] => 07400391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'System and method for detection of spatial signature yield loss' [patent_app_type] => utility [patent_app_number] => 11/675537 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400391.pdf [firstpage_image] =>[orig_patent_app_number] => 11675537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675537
System and method for detection of spatial signature yield loss Feb 14, 2007 Issued
Array ( [id] => 5070956 [patent_doc_number] => 20070192058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Method of measuring warpage of rear surface of substrate' [patent_app_type] => utility [patent_app_number] => 11/706331 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12254 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192058.pdf [firstpage_image] =>[orig_patent_app_number] => 11706331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706331
Method of measuring warpage of rear surface of substrate Feb 14, 2007 Issued
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