Search

Daniel A. Hess

Examiner (ID: 9166, Phone: (571)272-2392 , Office: P/2876 )

Most Active Art Unit
2876
Art Unit(s)
2876
Total Applications
2022
Issued Applications
1569
Pending Applications
141
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4582420 [patent_doc_number] => 07851254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'B-stageable die attach adhesives' [patent_app_type] => utility [patent_app_number] => 11/673140 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10432 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851254.pdf [firstpage_image] =>[orig_patent_app_number] => 11673140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673140
B-stageable die attach adhesives Feb 8, 2007 Issued
Array ( [id] => 247480 [patent_doc_number] => 07586235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Matching circuit for megasonic transducer device' [patent_app_type] => utility [patent_app_number] => 11/703893 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/586/07586235.pdf [firstpage_image] =>[orig_patent_app_number] => 11703893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703893
Matching circuit for megasonic transducer device Feb 6, 2007 Issued
Array ( [id] => 242082 [patent_doc_number] => 07587812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Electronic device manufacturing component with an embedded chip and methods of using the same' [patent_app_type] => utility [patent_app_number] => 11/672441 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587812.pdf [firstpage_image] =>[orig_patent_app_number] => 11672441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672441
Electronic device manufacturing component with an embedded chip and methods of using the same Feb 6, 2007 Issued
Array ( [id] => 4954992 [patent_doc_number] => 20080188016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Die detection and reference die wafermap alignment' [patent_app_type] => utility [patent_app_number] => 11/701681 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188016.pdf [firstpage_image] =>[orig_patent_app_number] => 11701681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701681
Die detection and reference die wafermap alignment Feb 1, 2007 Abandoned
Array ( [id] => 190791 [patent_doc_number] => 07642102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Real-time parameter tuning using wafer thickness' [patent_app_type] => utility [patent_app_number] => 11/668572 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 38010 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642102.pdf [firstpage_image] =>[orig_patent_app_number] => 11668572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668572
Real-time parameter tuning using wafer thickness Jan 29, 2007 Issued
Array ( [id] => 4845935 [patent_doc_number] => 20080182343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Real-Time Parameter Tuning Using Wafer Temperature' [patent_app_type] => utility [patent_app_number] => 11/668553 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 38007 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182343.pdf [firstpage_image] =>[orig_patent_app_number] => 11668553 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668553
Real-time parameter tuning using wafer temperature Jan 29, 2007 Issued
Array ( [id] => 5079697 [patent_doc_number] => 20070122921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Copper Wiring Module Control' [patent_app_type] => utility [patent_app_number] => 11/627353 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9194 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122921.pdf [firstpage_image] =>[orig_patent_app_number] => 11627353 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/627353
Copper wiring module control Jan 24, 2007 Issued
Array ( [id] => 348778 [patent_doc_number] => 07494893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'Identifying yield-relevant process parameters in integrated circuit device fabrication processes' [patent_app_type] => utility [patent_app_number] => 11/654391 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494893.pdf [firstpage_image] =>[orig_patent_app_number] => 11654391 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654391
Identifying yield-relevant process parameters in integrated circuit device fabrication processes Jan 16, 2007 Issued
Array ( [id] => 826805 [patent_doc_number] => 07402469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-22 [patent_title] => 'System and method for selectivity etching an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/652921 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3373 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402469.pdf [firstpage_image] =>[orig_patent_app_number] => 11652921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652921
System and method for selectivity etching an integrated circuit Jan 11, 2007 Issued
Array ( [id] => 4971340 [patent_doc_number] => 20070111342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'CHEMICAL MECHANICAL POLISHING TEST STRUCTURES AND METHODS FOR INSPECTING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/621512 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23448 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111342.pdf [firstpage_image] =>[orig_patent_app_number] => 11621512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621512
Chemical mechanical polishing test structures and methods for inspecting the same Jan 8, 2007 Issued
Array ( [id] => 5003589 [patent_doc_number] => 20070201156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'SUBSTRATE PROCESSING APPARATUS, PARAMETER MANAGEMENT SYSTEM FOR SUBSTRATE PROCESSING APPARATUS, PARAMETER MANAGEMENT METHOD FOR SUBSTRATE PROCESSING APPARATUS, PROGRAM, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 11/620261 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201156.pdf [firstpage_image] =>[orig_patent_app_number] => 11620261 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620261
Substrate processing apparatus, parameter management system for substrate processing apparatus, parameter management method for substrate processing apparatus, program, and storage medium Jan 4, 2007 Issued
Array ( [id] => 4915693 [patent_doc_number] => 20080096293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Method and Apparatus for Evaluation and Improvement of Mechanical and Thermal Properties of CNT/CNF Arrays' [patent_app_type] => utility [patent_app_number] => 11/618441 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5690 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096293.pdf [firstpage_image] =>[orig_patent_app_number] => 11618441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618441
Method and apparatus for evaluation and improvement of mechanical and thermal properties of CNT/CNF arrays Dec 28, 2006 Issued
Array ( [id] => 356174 [patent_doc_number] => 07488610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Insulator film characteristic measuring method and insulator film characteristic measuring apparatus' [patent_app_type] => utility [patent_app_number] => 11/645766 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488610.pdf [firstpage_image] =>[orig_patent_app_number] => 11645766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645766
Insulator film characteristic measuring method and insulator film characteristic measuring apparatus Dec 26, 2006 Issued
Array ( [id] => 847106 [patent_doc_number] => 07384806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method for characterizing defects on semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/614835 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7270 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384806.pdf [firstpage_image] =>[orig_patent_app_number] => 11614835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614835
Method for characterizing defects on semiconductor wafers Dec 20, 2006 Issued
Array ( [id] => 5213621 [patent_doc_number] => 20070102701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Structure and Method for Parallel Testing of Dies on a Semiconductor Wafer' [patent_app_type] => utility [patent_app_number] => 11/614241 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3727 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20070102701.pdf [firstpage_image] =>[orig_patent_app_number] => 11614241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614241
Structure and method for parallel testing of dies on a semiconductor wafer Dec 20, 2006 Issued
Array ( [id] => 5034773 [patent_doc_number] => 20070099312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'STRUCTURE AND METHOD FOR PARALLEL TESTING OF DIES ON A SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 11/614252 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3728 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099312.pdf [firstpage_image] =>[orig_patent_app_number] => 11614252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614252
Structure and method for parallel testing of dies on a semiconductor wafer Dec 20, 2006 Issued
Array ( [id] => 5031250 [patent_doc_number] => 20070095789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'METHOD FOR AUTOMATIC DETERMINATION OF SEMICONDUCTOR PLASMA CHAMBER MATCHING AND SOURCE OF FAULT BY COMPREHENSIVE PLASMA MONITORING' [patent_app_type] => utility [patent_app_number] => 11/612961 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20070095789.pdf [firstpage_image] =>[orig_patent_app_number] => 11612961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612961
Method for automatic determination of semiconductor plasma chamber matching and source of fault by comprehensive plasma monitoring Dec 18, 2006 Issued
Array ( [id] => 5253367 [patent_doc_number] => 20070134823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'ATOMIC LAYER DEPOSITION EQUIPMENT AND METHOD' [patent_app_type] => utility [patent_app_number] => 11/609862 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20070134823.pdf [firstpage_image] =>[orig_patent_app_number] => 11609862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609862
Atomic layer deposition equipment and method Dec 11, 2006 Issued
Array ( [id] => 4495768 [patent_doc_number] => 07947585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/090891 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/947/07947585.pdf [firstpage_image] =>[orig_patent_app_number] => 12090891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090891
Method of manufacturing semiconductor device Dec 3, 2006 Issued
Array ( [id] => 881166 [patent_doc_number] => 07355266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Semiconductor wafer test system' [patent_app_type] => utility [patent_app_number] => 11/607909 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 9939 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355266.pdf [firstpage_image] =>[orig_patent_app_number] => 11607909 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607909
Semiconductor wafer test system Dec 3, 2006 Issued
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