Search

Daniel A. Hess

Examiner (ID: 9166, Phone: (571)272-2392 , Office: P/2876 )

Most Active Art Unit
2876
Art Unit(s)
2876
Total Applications
2022
Issued Applications
1569
Pending Applications
141
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7450045 [patent_doc_number] => 20040067605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Semiconductor device having additional functional element and method of manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/673401 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2623 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067605.pdf [firstpage_image] =>[orig_patent_app_number] => 10673401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/673401
Semiconductor device having additional functional element and method of manufacturing thereof Sep 29, 2003 Issued
Array ( [id] => 7116748 [patent_doc_number] => 20050070049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method for fabricating wafer-level chip scale packages' [patent_app_type] => utility [patent_app_number] => 10/671771 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1720 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070049.pdf [firstpage_image] =>[orig_patent_app_number] => 10671771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/671771
Method for fabricating wafer-level chip scale packages Sep 28, 2003 Abandoned
Array ( [id] => 935361 [patent_doc_number] => 06974710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Fabrication method of semiconductor integrated circuit device and testing method' [patent_app_type] => utility [patent_app_number] => 10/670352 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9151 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974710.pdf [firstpage_image] =>[orig_patent_app_number] => 10670352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/670352
Fabrication method of semiconductor integrated circuit device and testing method Sep 25, 2003 Issued
Array ( [id] => 7269970 [patent_doc_number] => 20040058488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Monitoring system comprising infrared thermopile detetor' [patent_app_type] => new [patent_app_number] => 10/668489 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4387 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058488.pdf [firstpage_image] =>[orig_patent_app_number] => 10668489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/668489
Monitoring system comprising infrared thermopile detector Sep 22, 2003 Issued
Array ( [id] => 7130245 [patent_doc_number] => 20040041274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Versatile system for diffusion limiting void formation' [patent_app_type] => new [patent_app_number] => 10/662302 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041274.pdf [firstpage_image] =>[orig_patent_app_number] => 10662302 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/662302
Versatile system for diffusion limiting void formation Sep 15, 2003 Issued
Array ( [id] => 7465722 [patent_doc_number] => 20040166679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'System and method for monitoring contamination' [patent_app_type] => new [patent_app_number] => 10/662892 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 19863 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166679.pdf [firstpage_image] =>[orig_patent_app_number] => 10662892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/662892
System and method for monitoring contamination Sep 14, 2003 Issued
Array ( [id] => 1057669 [patent_doc_number] => 06856403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Optically stimulated electron emission contamination monitor and method' [patent_app_type] => utility [patent_app_number] => 10/662161 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3007 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856403.pdf [firstpage_image] =>[orig_patent_app_number] => 10662161 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/662161
Optically stimulated electron emission contamination monitor and method Sep 10, 2003 Issued
Array ( [id] => 7352684 [patent_doc_number] => 20040048398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Mask repair with electron beam-induced chemical etching' [patent_app_type] => new [patent_app_number] => 10/659961 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20040048398.pdf [firstpage_image] =>[orig_patent_app_number] => 10659961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659961
Method of repairing an opaque defect on a mask with electron beam-induced chemical etching Sep 9, 2003 Issued
Array ( [id] => 7212472 [patent_doc_number] => 20050054125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method and apparatus for thermally assisted testing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/655892 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3405 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20050054125.pdf [firstpage_image] =>[orig_patent_app_number] => 10655892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655892
Method and apparatus for thermally assisted testing of integrated circuits Sep 3, 2003 Issued
Array ( [id] => 7154504 [patent_doc_number] => 20050082649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Package for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/651522 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082649.pdf [firstpage_image] =>[orig_patent_app_number] => 10651522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651522
Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area Aug 28, 2003 Issued
Array ( [id] => 7212476 [patent_doc_number] => 20050054126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'System and method for marking the surface of a semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/651771 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20050054126.pdf [firstpage_image] =>[orig_patent_app_number] => 10651771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651771
System and method for marking the surface of a semiconductor package Aug 28, 2003 Abandoned
Array ( [id] => 7408542 [patent_doc_number] => 20040106223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Optical component and manufacturing method thereof, microlens substrate and manufacturing method thereof, display device, and imaging device' [patent_app_type] => new [patent_app_number] => 10/649891 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8989 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106223.pdf [firstpage_image] =>[orig_patent_app_number] => 10649891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649891
Optical component and manufacturing method thereof, microlens substrate and manufacturing method thereof, display device, and imaging device Aug 27, 2003 Issued
Array ( [id] => 7675192 [patent_doc_number] => 20040126926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/649741 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126926.pdf [firstpage_image] =>[orig_patent_app_number] => 10649741 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649741
Semiconductor device and method for fabricating the same Aug 27, 2003 Issued
Array ( [id] => 779160 [patent_doc_number] => 06995027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Integrated semiconductor structure for reliability tests of dielectrics' [patent_app_type] => utility [patent_app_number] => 10/649051 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7053 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995027.pdf [firstpage_image] =>[orig_patent_app_number] => 10649051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649051
Integrated semiconductor structure for reliability tests of dielectrics Aug 26, 2003 Issued
Array ( [id] => 1115475 [patent_doc_number] => 06800496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Characterization methodology for the thin gate oxide device' [patent_app_type] => B1 [patent_app_number] => 10/644322 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800496.pdf [firstpage_image] =>[orig_patent_app_number] => 10644322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/644322
Characterization methodology for the thin gate oxide device Aug 19, 2003 Issued
Array ( [id] => 557509 [patent_doc_number] => 07157368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Method of accelerating test of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/642222 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7011 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157368.pdf [firstpage_image] =>[orig_patent_app_number] => 10642222 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642222
Method of accelerating test of semiconductor device Aug 17, 2003 Issued
Array ( [id] => 7167105 [patent_doc_number] => 20040077109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods' [patent_app_type] => new [patent_app_number] => 10/642908 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5629 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20040077109.pdf [firstpage_image] =>[orig_patent_app_number] => 10642908 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642908
Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods Aug 17, 2003 Issued
Array ( [id] => 948791 [patent_doc_number] => 06962827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/640322 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6056 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/962/06962827.pdf [firstpage_image] =>[orig_patent_app_number] => 10640322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640322
Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device Aug 13, 2003 Issued
Array ( [id] => 919691 [patent_doc_number] => 07320935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Semiconductor device using an interconnect' [patent_app_type] => utility [patent_app_number] => 10/635892 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7742 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320935.pdf [firstpage_image] =>[orig_patent_app_number] => 10635892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635892
Semiconductor device using an interconnect Aug 4, 2003 Issued
Array ( [id] => 1034351 [patent_doc_number] => 06875560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Testing multiple levels in integrated circuit technology development' [patent_app_type] => utility [patent_app_number] => 10/632471 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875560.pdf [firstpage_image] =>[orig_patent_app_number] => 10632471 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632471
Testing multiple levels in integrated circuit technology development Jul 31, 2003 Issued
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