Search

Daniel C. Chappell

Examiner (ID: 2672, Phone: (571)272-5003 , Office: P/2135 )

Most Active Art Unit
2135
Art Unit(s)
2185, 2135
Total Applications
662
Issued Applications
506
Pending Applications
52
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19466256 [patent_doc_number] => 20240319926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DATA PROTECTION METHOD FOR MEMORY AND STORAGE DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/735961 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735961
Data protection method for memory and storage device thereof Jun 5, 2024 Issued
Array ( [id] => 20790007 [patent_doc_number] => 12663922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Deferred adaptive compression using computational storage for energy savings [patent_app_type] => utility [patent_app_number] => 18/734470 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734470
Deferred adaptive compression using computational storage for energy savings Jun 4, 2024 Issued
Array ( [id] => 19466242 [patent_doc_number] => 20240319912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => OPERATION BASED ON CONSOLIDATED MEMORY REGION DESCRIPTION DATA [patent_app_type] => utility [patent_app_number] => 18/733495 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733495
Operation based on consolidated memory region description data Jun 3, 2024 Issued
Array ( [id] => 19466245 [patent_doc_number] => 20240319915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/731348 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731348
DATA CODING DEVICE, MEMORY CONTROLLER, AND STORAGE DEVICE Jun 2, 2024 Pending
Array ( [id] => 20265719 [patent_doc_number] => 12436710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Techniques for sequential access operations [patent_app_type] => utility [patent_app_number] => 18/663980 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663980
Techniques for sequential access operations May 13, 2024 Issued
Array ( [id] => 20773295 [patent_doc_number] => 12656968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Processing-in-memory (PIM) high bandwidth memory (HBM) devices including PIM dynamic random access memory (DRAM) dies [patent_app_type] => utility [patent_app_number] => 18/650412 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 10180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650412
Processing-in-memory (PIM) high bandwidth memory (HBM) devices including PIM dynamic random access memory (DRAM) dies Apr 29, 2024 Issued
Array ( [id] => 20323020 [patent_doc_number] => 20250335108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => STORAGE SYSTEM WITH ADAPTIVE POWER CONTROL FUNCTIONALITY [patent_app_type] => utility [patent_app_number] => 18/651354 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/651354
STORAGE SYSTEM WITH ADAPTIVE POWER CONTROL FUNCTIONALITY Apr 29, 2024 Pending
Array ( [id] => 20273592 [patent_doc_number] => 12443373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Near memory processing dual in-line memory module and method for operating the same [patent_app_type] => utility [patent_app_number] => 18/628917 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2275 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628917
Near memory processing dual in-line memory module and method for operating the same Apr 7, 2024 Issued
Array ( [id] => 20331386 [patent_doc_number] => 12461661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Dynamic block categorization to improve reliability and performance in memory sub-system [patent_app_type] => utility [patent_app_number] => 18/624657 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624657
Dynamic block categorization to improve reliability and performance in memory sub-system Apr 1, 2024 Issued
Array ( [id] => 20757998 [patent_doc_number] => 12650767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Data receiving method and data receiving device [patent_app_type] => utility [patent_app_number] => 18/625147 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625147
Data receiving method and data receiving device Apr 1, 2024 Issued
Array ( [id] => 19303078 [patent_doc_number] => 20240231657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => DATA PROCESSING METHOD AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/617005 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617005 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617005
Data processing method and storage system Mar 25, 2024 Issued
Array ( [id] => 20415594 [patent_doc_number] => 12498879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Duplicate write circuit [patent_app_type] => utility [patent_app_number] => 18/611951 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611951
Duplicate write circuit Mar 20, 2024 Issued
Array ( [id] => 20666380 [patent_doc_number] => 12608155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Method and device for data access, electronic apparatus and storage medium [patent_app_type] => utility [patent_app_number] => 18/612543 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 8852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612543
Method and device for data access, electronic apparatus and storage medium Mar 20, 2024 Issued
Array ( [id] => 19450910 [patent_doc_number] => 20240311040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => AGGREGATING LOG DATA TO A REDUNDANT DIE OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/586861 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586861
Aggregating log data to a redundant die of a memory sub-system Feb 25, 2024 Issued
Array ( [id] => 19250919 [patent_doc_number] => 20240201909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SYSTEMS, METHODS, AND DEVICES FOR ACCELERATORS WITH VIRTUALIZATION AND TIERED MEMORY [patent_app_type] => utility [patent_app_number] => 18/587929 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587929
Systems, methods, and devices for accelerators with virtualization and tiered memory Feb 25, 2024 Issued
Array ( [id] => 20702910 [patent_doc_number] => 12625621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Data storage device and method of operating the same using primary and secondary indexes [patent_app_type] => utility [patent_app_number] => 18/432077 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432077
Data storage device and method of operating the same using primary and secondary indexes Feb 4, 2024 Issued
Array ( [id] => 19694826 [patent_doc_number] => 20250013371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/422316 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422316
Storage device and operating method thereof Jan 24, 2024 Issued
Array ( [id] => 20242907 [patent_doc_number] => 12423227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Generating virtual blocks using partial good blocks [patent_app_type] => utility [patent_app_number] => 18/411940 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4962 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411940
Generating virtual blocks using partial good blocks Jan 11, 2024 Issued
Array ( [id] => 20242902 [patent_doc_number] => 12423222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory devices [patent_app_type] => utility [patent_app_number] => 18/411473 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8938 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411473
Memory devices Jan 11, 2024 Issued
Array ( [id] => 19174375 [patent_doc_number] => 20240160349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => VIRTUAL MANAGEMENT UNIT SCHEME FOR TWO-PASS PROGRAMMING IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/409661 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409661
Virtual management unit scheme for two-pass programming in a memory sub-system Jan 9, 2024 Issued
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