Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1094253 [patent_doc_number] => 06825691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Apparatus and method for a radiation resistant latch with integrated scan' [patent_app_type] => B1 [patent_app_number] => 10/455163 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825691.pdf [firstpage_image] =>[orig_patent_app_number] => 10455163 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455163
Apparatus and method for a radiation resistant latch with integrated scan Jun 4, 2003 Issued
Array ( [id] => 1094263 [patent_doc_number] => 06825695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Unified local clock buffer structures' [patent_app_type] => B1 [patent_app_number] => 10/455170 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11993 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825695.pdf [firstpage_image] =>[orig_patent_app_number] => 10455170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455170
Unified local clock buffer structures Jun 4, 2003 Issued
Array ( [id] => 7339677 [patent_doc_number] => 20040246021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Modable dynamic terminator for high speed digital communications' [patent_app_type] => new [patent_app_number] => 10/455166 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3399 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246021.pdf [firstpage_image] =>[orig_patent_app_number] => 10455166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455166
Modable dynamic terminator for high speed digital communications Jun 4, 2003 Issued
Array ( [id] => 1044469 [patent_doc_number] => 06867616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Programmable logic device serial interface having dual-use phase-locked loop circuitry' [patent_app_type] => utility [patent_app_number] => 10/455773 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3778 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867616.pdf [firstpage_image] =>[orig_patent_app_number] => 10455773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455773
Programmable logic device serial interface having dual-use phase-locked loop circuitry Jun 3, 2003 Issued
Array ( [id] => 7621974 [patent_doc_number] => 06977527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Method and apparatus for suppressing spurious values in a differential output current' [patent_app_type] => utility [patent_app_number] => 10/455261 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4263 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977527.pdf [firstpage_image] =>[orig_patent_app_number] => 10455261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455261
Method and apparatus for suppressing spurious values in a differential output current Jun 3, 2003 Issued
Array ( [id] => 1141073 [patent_doc_number] => 06781226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Reconfigurable processor module comprising hybrid stacked integrated circuit die elements' [patent_app_type] => B2 [patent_app_number] => 10/452113 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2919 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781226.pdf [firstpage_image] =>[orig_patent_app_number] => 10452113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452113
Reconfigurable processor module comprising hybrid stacked integrated circuit die elements Jun 1, 2003 Issued
Array ( [id] => 7395392 [patent_doc_number] => 20040174197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Logic circuit, timing generator circuit, display device, portable terminal' [patent_app_type] => new [patent_app_number] => 10/485374 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6023 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174197.pdf [firstpage_image] =>[orig_patent_app_number] => 10485374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/485374
Logic circuit, timing generation circuit, display device, and portable terminal May 29, 2003 Issued
Array ( [id] => 779913 [patent_doc_number] => 06995583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Structure and method for dynamic control of output driver voltage' [patent_app_type] => utility [patent_app_number] => 10/448762 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4133 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995583.pdf [firstpage_image] =>[orig_patent_app_number] => 10448762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448762
Structure and method for dynamic control of output driver voltage May 29, 2003 Issued
Array ( [id] => 1044467 [patent_doc_number] => 06867615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Dedicated input/output first in/first out module for a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 10/452764 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867615.pdf [firstpage_image] =>[orig_patent_app_number] => 10452764 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452764
Dedicated input/output first in/first out module for a field programmable gate array May 29, 2003 Issued
Array ( [id] => 6703203 [patent_doc_number] => 20030226083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit' [patent_app_type] => new [patent_app_number] => 10/448076 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12950 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20030226083.pdf [firstpage_image] =>[orig_patent_app_number] => 10448076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448076
Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit May 29, 2003 Issued
Array ( [id] => 7342036 [patent_doc_number] => 20040246613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Voltage mode current-assisted pre-emphasis driver' [patent_app_type] => new [patent_app_number] => 10/445167 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246613.pdf [firstpage_image] =>[orig_patent_app_number] => 10445167 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445167
Voltage mode current-assisted pre-emphasis driver May 22, 2003 Issued
Array ( [id] => 976339 [patent_doc_number] => 06933746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method and apparatus for coupling an input node to an output node' [patent_app_type] => utility [patent_app_number] => 10/442367 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933746.pdf [firstpage_image] =>[orig_patent_app_number] => 10442367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442367
Method and apparatus for coupling an input node to an output node May 20, 2003 Issued
Array ( [id] => 7273494 [patent_doc_number] => 20040232945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Current mode logic driver that employs a level shifting mechanism' [patent_app_type] => new [patent_app_number] => 10/445171 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232945.pdf [firstpage_image] =>[orig_patent_app_number] => 10445171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445171
Current mode logic driver that employs a level shifting mechanism May 19, 2003 Issued
Array ( [id] => 1009898 [patent_doc_number] => 06900662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Level translator circuit for power supply disablement' [patent_app_type] => utility [patent_app_number] => 10/439362 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2113 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900662.pdf [firstpage_image] =>[orig_patent_app_number] => 10439362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439362
Level translator circuit for power supply disablement May 15, 2003 Issued
Array ( [id] => 7409575 [patent_doc_number] => 20040227542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Digital logic with reduced leakage' [patent_app_type] => new [patent_app_number] => 10/437764 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2506 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227542.pdf [firstpage_image] =>[orig_patent_app_number] => 10437764 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437764
Digital logic with reduced leakage May 13, 2003 Issued
Array ( [id] => 1015294 [patent_doc_number] => 06894527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Evolved circuits for bitstream protection' [patent_app_type] => utility [patent_app_number] => 10/436971 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894527.pdf [firstpage_image] =>[orig_patent_app_number] => 10436971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436971
Evolved circuits for bitstream protection May 11, 2003 Issued
Array ( [id] => 1047695 [patent_doc_number] => 06864720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Semiconductor integrated circuit and circuit designating system' [patent_app_type] => utility [patent_app_number] => 10/428762 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4807 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864720.pdf [firstpage_image] =>[orig_patent_app_number] => 10428762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428762
Semiconductor integrated circuit and circuit designating system May 4, 2003 Issued
Array ( [id] => 1015300 [patent_doc_number] => 06894530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Programmable and fixed logic circuitry for high-speed interfaces' [patent_app_type] => utility [patent_app_number] => 10/425862 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7792 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894530.pdf [firstpage_image] =>[orig_patent_app_number] => 10425862 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425862
Programmable and fixed logic circuitry for high-speed interfaces Apr 27, 2003 Issued
Array ( [id] => 7612262 [patent_doc_number] => 06903575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Scalable device architecture for high-speed interfaces' [patent_app_type] => utility [patent_app_number] => 10/425863 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903575.pdf [firstpage_image] =>[orig_patent_app_number] => 10425863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425863
Scalable device architecture for high-speed interfaces Apr 27, 2003 Issued
Array ( [id] => 760003 [patent_doc_number] => 07015718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Register file apparatus and method for computing flush masks in a multi-threaded processing system' [patent_app_type] => utility [patent_app_number] => 10/422684 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3173 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015718.pdf [firstpage_image] =>[orig_patent_app_number] => 10422684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422684
Register file apparatus and method for computing flush masks in a multi-threaded processing system Apr 20, 2003 Issued
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