
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1009902
[patent_doc_number] => 06900666
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Dual threshold voltage and low swing domino logic circuits'
[patent_app_type] => utility
[patent_app_number] => 10/411375
[patent_app_country] => US
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[pdf_file] => patents/06/900/06900666.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/411375 | Dual threshold voltage and low swing domino logic circuits | Apr 10, 2003 | Issued |
Array
(
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[patent_doc_number] => 20030231077
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[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Transpinnor-based transmission line transceivers and applications'
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2005-11-08
[patent_title] => 'Programmable differential internal termination for a low voltage differential signal input or output buffer'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/409891 | Programmable differential internal termination for a low voltage differential signal input or output buffer | Apr 7, 2003 | Issued |
Array
(
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[patent_issue_date] => 2005-11-22
[patent_title] => 'Electronic circuit with on-chip programmable terminations'
[patent_app_type] => utility
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[patent_app_country] => US
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Array
(
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Array
(
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[patent_title] => 'FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections'
[patent_app_type] => reissue
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/392751 | FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections | Mar 19, 2003 | Issued |
Array
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[patent_title] => 'Specialized programmable logic region with low-power mode'
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Array
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[patent_title] => 'Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting'
[patent_app_type] => B2
[patent_app_number] => 10/360268
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Array
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Array
(
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[patent_title] => 'Interface device and information processing system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/357215 | Interface device and information processing system | Feb 3, 2003 | Issued |
Array
(
[id] => 540400
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[patent_title] => 'Signal transmission system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/353040 | Signal transmission system | Jan 28, 2003 | Issued |
Array
(
[id] => 7320363
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[patent_title] => 'High voltage level translator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263512 | High voltage level translator | Jan 12, 2003 | Issued |
Array
(
[id] => 6631384
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340104 | High speed digital signal buffer and method | Jan 9, 2003 | Issued |
| 10/337272 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING HIGH-SPEED AND LOW-POWER LOGIC GATES WITH COMMON TRANSISTOR SUBSTRATE POTENTIALS, DESIGN METHODS THEREOF, AND RELATED PROGRAM RECORDING MEDIUM | Jan 6, 2003 | Abandoned |
Array
(
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[patent_title] => 'Dynamic node keeper system and method'
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[firstpage_image] =>[orig_patent_app_number] => 10334264
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/334264 | Dynamic node keeper system and method | Dec 30, 2002 | Issued |
Array
(
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Array
(
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[patent_title] => 'AC powered logic circuitry'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328461 | AC powered logic circuitry | Dec 22, 2002 | Issued |
Array
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Array
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