Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1009902 [patent_doc_number] => 06900666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Dual threshold voltage and low swing domino logic circuits' [patent_app_type] => utility [patent_app_number] => 10/411375 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 9693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900666.pdf [firstpage_image] =>[orig_patent_app_number] => 10411375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411375
Dual threshold voltage and low swing domino logic circuits Apr 10, 2003 Issued
Array ( [id] => 6803683 [patent_doc_number] => 20030231077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Transpinnor-based transmission line transceivers and applications' [patent_app_type] => new [patent_app_number] => 10/411073 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15154 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20030231077.pdf [firstpage_image] =>[orig_patent_app_number] => 10411073 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411073
Transpinnor-based transmission line transceivers and applications Apr 8, 2003 Issued
Array ( [id] => 949183 [patent_doc_number] => 06963219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Programmable differential internal termination for a low voltage differential signal input or output buffer' [patent_app_type] => utility [patent_app_number] => 10/409891 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7540 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963219.pdf [firstpage_image] =>[orig_patent_app_number] => 10409891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/409891
Programmable differential internal termination for a low voltage differential signal input or output buffer Apr 7, 2003 Issued
Array ( [id] => 944446 [patent_doc_number] => 06967500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Electronic circuit with on-chip programmable terminations' [patent_app_type] => utility [patent_app_number] => 10/397669 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4407 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967500.pdf [firstpage_image] =>[orig_patent_app_number] => 10397669 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397669
Electronic circuit with on-chip programmable terminations Mar 25, 2003 Issued
Array ( [id] => 6807589 [patent_doc_number] => 20030197528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Bidirectional signal transmission circuit and bus system' [patent_app_type] => new [patent_app_number] => 10/394677 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10857 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197528.pdf [firstpage_image] =>[orig_patent_app_number] => 10394677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/394677
Bidirectional signal transmission circuit and bus system Mar 20, 2003 Issued
Array ( [id] => 507788 [patent_doc_number] => RE039510 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2007-03-13 [patent_title] => 'FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections' [patent_app_type] => reissue [patent_app_number] => 10/392751 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 26216 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/039/RE039510.pdf [firstpage_image] =>[orig_patent_app_number] => 10392751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/392751
FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections Mar 19, 2003 Issued
Array ( [id] => 1211302 [patent_doc_number] => 06714042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Specialized programmable logic region with low-power mode' [patent_app_type] => B1 [patent_app_number] => 10/384905 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1974 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714042.pdf [firstpage_image] =>[orig_patent_app_number] => 10384905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/384905
Specialized programmable logic region with low-power mode Mar 5, 2003 Issued
Array ( [id] => 1171142 [patent_doc_number] => 06756810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting' [patent_app_type] => B2 [patent_app_number] => 10/360268 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3850 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756810.pdf [firstpage_image] =>[orig_patent_app_number] => 10360268 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360268
Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting Feb 5, 2003 Issued
Array ( [id] => 6680946 [patent_doc_number] => 20030116810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Programmable impedance control circuit' [patent_app_type] => new [patent_app_number] => 10/357841 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20030116810.pdf [firstpage_image] =>[orig_patent_app_number] => 10357841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357841
Programmable impedance control circuit Feb 3, 2003 Issued
Array ( [id] => 664455 [patent_doc_number] => 07102388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Interface device and information processing system' [patent_app_type] => utility [patent_app_number] => 10/357215 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102388.pdf [firstpage_image] =>[orig_patent_app_number] => 10357215 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357215
Interface device and information processing system Feb 3, 2003 Issued
Array ( [id] => 540400 [patent_doc_number] => 07173449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Signal transmission system' [patent_app_type] => utility [patent_app_number] => 10/353040 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 11576 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173449.pdf [firstpage_image] =>[orig_patent_app_number] => 10353040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353040
Signal transmission system Jan 28, 2003 Issued
Array ( [id] => 7320363 [patent_doc_number] => 20040136130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'High voltage level translator' [patent_app_type] => new [patent_app_number] => 10/263512 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5564 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136130.pdf [firstpage_image] =>[orig_patent_app_number] => 10263512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263512
High voltage level translator Jan 12, 2003 Issued
Array ( [id] => 6631384 [patent_doc_number] => 20030102891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'High speed digital signal buffer and method' [patent_app_type] => new [patent_app_number] => 10/340104 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3589 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20030102891.pdf [firstpage_image] =>[orig_patent_app_number] => 10340104 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/340104
High speed digital signal buffer and method Jan 9, 2003 Issued
10/337272 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING HIGH-SPEED AND LOW-POWER LOGIC GATES WITH COMMON TRANSISTOR SUBSTRATE POTENTIALS, DESIGN METHODS THEREOF, AND RELATED PROGRAM RECORDING MEDIUM Jan 6, 2003 Abandoned
Array ( [id] => 969036 [patent_doc_number] => 06940314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-06 [patent_title] => 'Dynamic node keeper system and method' [patent_app_type] => utility [patent_app_number] => 10/334264 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940314.pdf [firstpage_image] =>[orig_patent_app_number] => 10334264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334264
Dynamic node keeper system and method Dec 30, 2002 Issued
Array ( [id] => 1019025 [patent_doc_number] => 06891396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks' [patent_app_type] => utility [patent_app_number] => 10/330672 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5617 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891396.pdf [firstpage_image] =>[orig_patent_app_number] => 10330672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330672
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks Dec 26, 2002 Issued
Array ( [id] => 677462 [patent_doc_number] => 07088145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'AC powered logic circuitry' [patent_app_type] => utility [patent_app_number] => 10/328461 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5896 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088145.pdf [firstpage_image] =>[orig_patent_app_number] => 10328461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328461
AC powered logic circuitry Dec 22, 2002 Issued
Array ( [id] => 7616567 [patent_doc_number] => 06946875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Universal logic module and ASIC using the same' [patent_app_type] => utility [patent_app_number] => 10/325572 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7152 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946875.pdf [firstpage_image] =>[orig_patent_app_number] => 10325572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325572
Universal logic module and ASIC using the same Dec 18, 2002 Issued
Array ( [id] => 1320270 [patent_doc_number] => 06608501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Hi gain clock circuit' [patent_app_type] => B2 [patent_app_number] => 10/320466 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3780 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/608/06608501.pdf [firstpage_image] =>[orig_patent_app_number] => 10320466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320466
Hi gain clock circuit Dec 16, 2002 Issued
Array ( [id] => 1341901 [patent_doc_number] => 06593770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method and device for active impedance matching' [patent_app_type] => B2 [patent_app_number] => 10/317887 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6874 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593770.pdf [firstpage_image] =>[orig_patent_app_number] => 10317887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/317887
Method and device for active impedance matching Dec 11, 2002 Issued
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