
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7286964
[patent_doc_number] => 20040108873
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[patent_issue_date] => 2004-06-10
[patent_title] => 'Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic'
[patent_app_type] => new
[patent_app_number] => 10/314962
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/314962 | Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic | Dec 9, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-05-22
[patent_title] => 'Method and apparatus for dynamically controlling the performance of buffers under different performance conditions'
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Array
(
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[patent_issue_date] => 2004-09-07
[patent_title] => 'Variable voltage tolerant input/output circuit'
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Array
(
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[patent_issue_date] => 2003-11-20
[patent_title] => 'Bulk input differential logic circuit'
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Array
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[patent_title] => 'FPGA lookup table with high speed read decorder'
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Array
(
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Array
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[patent_title] => 'Monotonic Dynamic-Static Pseudo-NMOS Logic Circuit'
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Array
(
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[patent_issue_date] => 2004-08-24
[patent_title] => 'Buffer driver circuit for producing a fast, stable, and accurate reference voltage'
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Array
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[id] => 6748414
[patent_doc_number] => 20030042934
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[patent_title] => 'Clocked half-rail differential logic'
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Array
(
[id] => 7160831
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[patent_title] => 'Terminating resistor driver for high speed data communication'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/065475 | Terminating resistor driver for high speed data communication | Oct 21, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/278355 | Method for clock control of half-rail differential logic | Oct 21, 2002 | Issued |
Array
(
[id] => 1182791
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Array
(
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[patent_title] => 'Power supply decoupling for parallel terminated transmission line'
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255471 | Method of transparently reducing power consumption of a high-speed communication link | Sep 25, 2002 | Issued |