Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7286964 [patent_doc_number] => 20040108873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic' [patent_app_type] => new [patent_app_number] => 10/314962 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20040108873.pdf [firstpage_image] =>[orig_patent_app_number] => 10314962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314962
Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic Dec 9, 2002 Issued
Array ( [id] => 6799823 [patent_doc_number] => 20030094987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method and apparatus for dynamically controlling the performance of buffers under different performance conditions' [patent_app_type] => new [patent_app_number] => 10/315973 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7104 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094987.pdf [firstpage_image] =>[orig_patent_app_number] => 10315973 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315973
Method and apparatus for dynamically controlling the performance of buffers under different performance conditions Dec 8, 2002 Issued
Array ( [id] => 1133454 [patent_doc_number] => 06788107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Variable voltage tolerant input/output circuit' [patent_app_type] => B2 [patent_app_number] => 10/313572 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2331 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788107.pdf [firstpage_image] =>[orig_patent_app_number] => 10313572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313572
Variable voltage tolerant input/output circuit Dec 5, 2002 Issued
Array ( [id] => 6768387 [patent_doc_number] => 20030214327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Bulk input differential logic circuit' [patent_app_type] => new [patent_app_number] => 10/307371 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6586 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214327.pdf [firstpage_image] =>[orig_patent_app_number] => 10307371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307371
Bulk input differential logic circuit Dec 1, 2002 Issued
Array ( [id] => 1307159 [patent_doc_number] => 06621296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'FPGA lookup table with high speed read decorder' [patent_app_type] => B2 [patent_app_number] => 10/295713 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 10938 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621296.pdf [firstpage_image] =>[orig_patent_app_number] => 10295713 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/295713
FPGA lookup table with high speed read decorder Nov 14, 2002 Issued
Array ( [id] => 1237615 [patent_doc_number] => 06690202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Correction of duty-cycle distortion in communications and other circuits' [patent_app_type] => B1 [patent_app_number] => 10/294254 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3329 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690202.pdf [firstpage_image] =>[orig_patent_app_number] => 10294254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/294254
Correction of duty-cycle distortion in communications and other circuits Nov 12, 2002 Issued
Array ( [id] => 6778829 [patent_doc_number] => 20030049910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Monotonic Dynamic-Static Pseudo-NMOS Logic Circuit' [patent_app_type] => new [patent_app_number] => 10/283775 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4745 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049910.pdf [firstpage_image] =>[orig_patent_app_number] => 10283775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283775
Monotonic dynamic-static pseudo-NMOS logic circuit Oct 28, 2002 Issued
Array ( [id] => 1142225 [patent_doc_number] => 06781417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Buffer driver circuit for producing a fast, stable, and accurate reference voltage' [patent_app_type] => B1 [patent_app_number] => 10/282459 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4033 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781417.pdf [firstpage_image] =>[orig_patent_app_number] => 10282459 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282459
Buffer driver circuit for producing a fast, stable, and accurate reference voltage Oct 28, 2002 Issued
Array ( [id] => 6748414 [patent_doc_number] => 20030042934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Clocked half-rail differential logic' [patent_app_type] => new [patent_app_number] => 10/278329 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7166 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042934.pdf [firstpage_image] =>[orig_patent_app_number] => 10278329 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278329
Clocked half-rail differential logic Oct 21, 2002 Issued
Array ( [id] => 7160831 [patent_doc_number] => 20040075463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Terminating resistor driver for high speed data communication' [patent_app_type] => new [patent_app_number] => 10/065475 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075463.pdf [firstpage_image] =>[orig_patent_app_number] => 10065475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065475
Terminating resistor driver for high speed data communication Oct 21, 2002 Issued
Array ( [id] => 1289558 [patent_doc_number] => 06639429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method for clock control of half-rail differential logic' [patent_app_type] => B2 [patent_app_number] => 10/278355 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7160 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639429.pdf [firstpage_image] =>[orig_patent_app_number] => 10278355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278355
Method for clock control of half-rail differential logic Oct 21, 2002 Issued
Array ( [id] => 1182791 [patent_doc_number] => 06741094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Electronic apparatus test circuit' [patent_app_type] => B2 [patent_app_number] => 10/273170 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2311 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741094.pdf [firstpage_image] =>[orig_patent_app_number] => 10273170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273170
Electronic apparatus test circuit Oct 17, 2002 Issued
Array ( [id] => 1057221 [patent_doc_number] => 06856163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Power supply decoupling for parallel terminated transmission line' [patent_app_type] => utility [patent_app_number] => 10/271664 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1809 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856163.pdf [firstpage_image] =>[orig_patent_app_number] => 10271664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271664
Power supply decoupling for parallel terminated transmission line Oct 14, 2002 Issued
Array ( [id] => 6648230 [patent_doc_number] => 20030212940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Interface architecture for embedded field programmable gate array cores' [patent_app_type] => new [patent_app_number] => 10/270022 [patent_app_country] => US [patent_app_date] => 2002-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9350 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20030212940.pdf [firstpage_image] =>[orig_patent_app_number] => 10270022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270022
Interface architecture for embedded field programmable gate array cores Oct 11, 2002 Abandoned
Array ( [id] => 7207097 [patent_doc_number] => 20040070424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Decoder scheme for making large size decoder' [patent_app_type] => new [patent_app_number] => 10/269166 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070424.pdf [firstpage_image] =>[orig_patent_app_number] => 10269166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269166
Decoder scheme for making large size decoder Oct 9, 2002 Issued
Array ( [id] => 1226192 [patent_doc_number] => 06700413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Symmetric current mode logic' [patent_app_type] => B1 [patent_app_number] => 10/266671 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4772 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700413.pdf [firstpage_image] =>[orig_patent_app_number] => 10266671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266671
Symmetric current mode logic Oct 8, 2002 Issued
Array ( [id] => 6824043 [patent_doc_number] => 20030234665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Anti-fuse sense amplifier' [patent_app_type] => new [patent_app_number] => 10/262872 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3287 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20030234665.pdf [firstpage_image] =>[orig_patent_app_number] => 10262872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262872
Anti-fuse sense amplifier Oct 2, 2002 Abandoned
Array ( [id] => 6816368 [patent_doc_number] => 20030067326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Integrated logic circuit and hierarchical design method thereof' [patent_app_type] => new [patent_app_number] => 10/263071 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2155 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20030067326.pdf [firstpage_image] =>[orig_patent_app_number] => 10263071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263071
Integrated logic circuit and hierarchical design method thereof Oct 2, 2002 Issued
Array ( [id] => 7278760 [patent_doc_number] => 20040061137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Integrated circuit beta compensator for external interface circuitry' [patent_app_type] => new [patent_app_number] => 10/262579 [patent_app_country] => US [patent_app_date] => 2002-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3020 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061137.pdf [firstpage_image] =>[orig_patent_app_number] => 10262579 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262579
Integrated circuit beta compensator for external interface circuitry Sep 27, 2002 Issued
Array ( [id] => 1106795 [patent_doc_number] => 06812739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of transparently reducing power consumption of a high-speed communication link' [patent_app_type] => B2 [patent_app_number] => 10/255471 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2363 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812739.pdf [firstpage_image] =>[orig_patent_app_number] => 10255471 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255471
Method of transparently reducing power consumption of a high-speed communication link Sep 25, 2002 Issued
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