Daniel D. Chang

Array ( [id] => 6833085 [patent_doc_number] => 20030160630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Bidirectional edge accelerator circuit' [patent_app_type] => new [patent_app_number] => 10/083361 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3876 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20030160630.pdf [firstpage_image] =>[orig_patent_app_number] => 10083361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183925 [patent_doc_number] => 06737890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Switching circuit device' [patent_app_type] => B2 [patent_app_number] => 10/073363 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 3859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737890.pdf [firstpage_image] =>[orig_patent_app_number] => 10073363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368408 [patent_doc_number] => 20020118040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Logic level shifting circuit' [patent_app_type] => new [patent_app_number] => 10/074079 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4383 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118040.pdf [firstpage_image] =>[orig_patent_app_number] => 10074079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1282155 [patent_doc_number] => 06646468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Switching device with high-voltage translator' [patent_app_type] => B2 [patent_app_number] => 10/073680 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5418 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646468.pdf [firstpage_image] =>[orig_patent_app_number] => 10073680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1282136 [patent_doc_number] => 06646465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Programmable logic device including bi-directional shift register' [patent_app_type] => B2 [patent_app_number] => 10/072461 [patent_app_country] => US [patent_app_date] => 2002-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2127 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646465.pdf [firstpage_image] =>[orig_patent_app_number] => 10072461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6841427 [patent_doc_number] => 20030146774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'ASIC architechture for active-compensation of a programmable impedance I/O' [patent_app_type] => new [patent_app_number] => 10/072165 [patent_app_country] => US [patent_app_date] => 2002-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2837 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20030146774.pdf [firstpage_image] =>[orig_patent_app_number] => 10072165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1137476 [patent_doc_number] => 06784689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Transmission gate based signal transition accelerator' [patent_app_type] => B2 [patent_app_number] => 10/068671 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3489 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784689.pdf [firstpage_image] =>[orig_patent_app_number] => 10068671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1382628 [patent_doc_number] => 06563336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Signal shielding assignment technique for precharge based logic' [patent_app_type] => B1 [patent_app_number] => 10/071365 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563336.pdf [firstpage_image] =>[orig_patent_app_number] => 10071365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1114074 [patent_doc_number] => 06803793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Reduced swing charge recycling circuit arrangement and adder including the same' [patent_app_type] => B2 [patent_app_number] => 10/061379 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803793.pdf [firstpage_image] =>[orig_patent_app_number] => 10061379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6844486 [patent_doc_number] => 20030149833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Magnetoresistive memory for a complex programmable logic device' [patent_app_type] => new [patent_app_number] => 10/061660 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4759 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149833.pdf [firstpage_image] =>[orig_patent_app_number] => 10061660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7646884 [patent_doc_number] => 06476634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'ALU implementation in single PLD logic cell' [patent_app_type] => B1 [patent_app_number] => 10/061571 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6267 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476634.pdf [firstpage_image] =>[orig_patent_app_number] => 10061571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1181206 [patent_doc_number] => 06744276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Serial digital audio data port with multiple functional configurations' [patent_app_type] => B1 [patent_app_number] => 10/062076 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4617 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744276.pdf [firstpage_image] =>[orig_patent_app_number] => 10062076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1303450 [patent_doc_number] => 06624664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Clocked full-rail differential logic with sense amplifiers' [patent_app_type] => B2 [patent_app_number] => 10/060578 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6744 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624664.pdf [firstpage_image] =>[orig_patent_app_number] => 10060578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1315636 [patent_doc_number] => 06614264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method for increasing the load capacity of full-rail differential logic' [patent_app_type] => B2 [patent_app_number] => 10/060566 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6741 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 527 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614264.pdf [firstpage_image] =>[orig_patent_app_number] => 10060566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1094256 [patent_doc_number] => 06825692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Input buffer for multiple differential I/O standards' [patent_app_type] => B1 [patent_app_number] => 10/056367 [patent_app_country] => US [patent_app_date] => 2002-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8902 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825692.pdf [firstpage_image] =>[orig_patent_app_number] => 10056367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634160 [patent_doc_number] => 06657460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Spatially filtered data bus drivers and receivers and method of operating same' [patent_app_type] => B2 [patent_app_number] => 10/056762 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657460.pdf [firstpage_image] =>[orig_patent_app_number] => 10056762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1307151 [patent_doc_number] => 06621295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Reconfigurable priority encoding' [patent_app_type] => B1 [patent_app_number] => 10/047667 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3211 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621295.pdf [firstpage_image] =>[orig_patent_app_number] => 10047667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5933998 [patent_doc_number] => 20020060602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Bias voltage generator usable with circuit for producing low-voltage differential signals' [patent_app_type] => new [patent_app_number] => 10/047158 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5099 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060602.pdf [firstpage_image] =>[orig_patent_app_number] => 10047158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1121494 [patent_doc_number] => 06798237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'On-chip impedance matching circuit' [patent_app_type] => B1 [patent_app_number] => 10/044365 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5853 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798237.pdf [firstpage_image] =>[orig_patent_app_number] => 10044365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6854549 [patent_doc_number] => 20030128050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'FPGA and embedded circuitry initialization and processing' [patent_app_type] => new [patent_app_number] => 10/043769 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5687 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128050.pdf [firstpage_image] =>[orig_patent_app_number] => 10043769 [rel_patent_id] =>[rel_patent_doc_number] =>)