Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1307221 [patent_doc_number] => 06621305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Partial swing low power CMOS logic circuits' [patent_app_type] => B2 [patent_app_number] => 09/920886 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2504 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621305.pdf [firstpage_image] =>[orig_patent_app_number] => 09920886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920886
Partial swing low power CMOS logic circuits Aug 2, 2001 Issued
Array ( [id] => 1233004 [patent_doc_number] => 06693456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Interconnection network for a field programmable gate array' [patent_app_type] => B2 [patent_app_number] => 09/923294 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 8359 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693456.pdf [firstpage_image] =>[orig_patent_app_number] => 09923294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923294
Interconnection network for a field programmable gate array Aug 2, 2001 Issued
Array ( [id] => 1367011 [patent_doc_number] => 06573756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Active noise-canceling scheme for dynamic circuits' [patent_app_type] => B2 [patent_app_number] => 09/919785 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1966 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573756.pdf [firstpage_image] =>[orig_patent_app_number] => 09919785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919785
Active noise-canceling scheme for dynamic circuits Jul 30, 2001 Issued
Array ( [id] => 7077224 [patent_doc_number] => 20010040467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Method and apparatus for reducing soft errors in dynamic circuits' [patent_app_type] => new [patent_app_number] => 09/909104 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040467.pdf [firstpage_image] =>[orig_patent_app_number] => 09909104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909104
Method and apparatus for reducing soft errors in dynamic circuits Jul 17, 2001 Issued
Array ( [id] => 6124536 [patent_doc_number] => 20020075037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Digital interface with low power consumption' [patent_app_type] => new [patent_app_number] => 09/906594 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1832 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075037.pdf [firstpage_image] =>[orig_patent_app_number] => 09906594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906594
Digital interface with low power consumption Jul 16, 2001 Issued
Array ( [id] => 1421226 [patent_doc_number] => 06525558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Programmable impedance control circuit' [patent_app_type] => B2 [patent_app_number] => 09/905360 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525558.pdf [firstpage_image] =>[orig_patent_app_number] => 09905360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905360
Programmable impedance control circuit Jul 12, 2001 Issued
Array ( [id] => 1345717 [patent_doc_number] => 06590424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'High-throughput asynchronous dynamic pipelines' [patent_app_type] => B2 [patent_app_number] => 09/904278 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 17739 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590424.pdf [firstpage_image] =>[orig_patent_app_number] => 09904278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904278
High-throughput asynchronous dynamic pipelines Jul 11, 2001 Issued
Array ( [id] => 1591688 [patent_doc_number] => 06483347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'High speed digital signal buffer and method' [patent_app_type] => B1 [patent_app_number] => 09/904668 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3551 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483347.pdf [firstpage_image] =>[orig_patent_app_number] => 09904668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904668
High speed digital signal buffer and method Jul 10, 2001 Issued
Array ( [id] => 7646877 [patent_doc_number] => 06476641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Low power consuming circuit' [patent_app_type] => B2 [patent_app_number] => 09/898979 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476641.pdf [firstpage_image] =>[orig_patent_app_number] => 09898979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898979
Low power consuming circuit Jul 2, 2001 Issued
Array ( [id] => 6753847 [patent_doc_number] => 20030001623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Conditional burn-in keeper for dynamic circuits' [patent_app_type] => new [patent_app_number] => 09/896252 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1269 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001623.pdf [firstpage_image] =>[orig_patent_app_number] => 09896252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896252
Conditional burn-in keeper for dynamic circuits Jun 27, 2001 Issued
Array ( [id] => 6753846 [patent_doc_number] => 20030001622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Symmetric differential domino \"AND gate\"' [patent_app_type] => new [patent_app_number] => 09/892565 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4401 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001622.pdf [firstpage_image] =>[orig_patent_app_number] => 09892565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892565
Symmetric differential domino AND gate Jun 27, 2001 Issued
Array ( [id] => 1128972 [patent_doc_number] => 06791356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Bidirectional port with clock channel used for synchronization' [patent_app_type] => B2 [patent_app_number] => 09/894865 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8327 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791356.pdf [firstpage_image] =>[orig_patent_app_number] => 09894865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894865
Bidirectional port with clock channel used for synchronization Jun 27, 2001 Issued
Array ( [id] => 6753841 [patent_doc_number] => 20030001617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Input circuit with non-delayed time blanking' [patent_app_type] => new [patent_app_number] => 09/894187 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5607 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001617.pdf [firstpage_image] =>[orig_patent_app_number] => 09894187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894187
Input circuit with non-delayed time blanking Jun 26, 2001 Issued
Array ( [id] => 566161 [patent_doc_number] => 07157940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-02 [patent_title] => 'System and methods for a high-speed dynamic data bus' [patent_app_type] => utility [patent_app_number] => 09/888970 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6911 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157940.pdf [firstpage_image] =>[orig_patent_app_number] => 09888970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888970
System and methods for a high-speed dynamic data bus Jun 24, 2001 Issued
Array ( [id] => 5886384 [patent_doc_number] => 20020011881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Output buffer circuit' [patent_app_type] => new [patent_app_number] => 09/884757 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6789 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011881.pdf [firstpage_image] =>[orig_patent_app_number] => 09884757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884757
High integration-capable output buffer circuit unaffected by manufacturing process fluctuations or changes in use Jun 18, 2001 Issued
Array ( [id] => 1182822 [patent_doc_number] => 06741098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'High speed semiconductor circuit having low power consumption' [patent_app_type] => B2 [patent_app_number] => 09/884662 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4527 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741098.pdf [firstpage_image] =>[orig_patent_app_number] => 09884662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884662
High speed semiconductor circuit having low power consumption Jun 18, 2001 Issued
Array ( [id] => 6879741 [patent_doc_number] => 20010031027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Method and apparatus for high-speed edge-programmable timing signal generation' [patent_app_type] => new [patent_app_number] => 09/883613 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5791 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20010031027.pdf [firstpage_image] =>[orig_patent_app_number] => 09883613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883613
Method and apparatus for high-speed edge-programmable timing signal generation Jun 17, 2001 Issued
Array ( [id] => 1464085 [patent_doc_number] => 06351143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Content-addressable memory implemented using programmable logic' [patent_app_type] => B1 [patent_app_number] => 09/882615 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4795 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351143.pdf [firstpage_image] =>[orig_patent_app_number] => 09882615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882615
Content-addressable memory implemented using programmable logic Jun 14, 2001 Issued
Array ( [id] => 6985889 [patent_doc_number] => 20010035771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method and apparatus for limited reprogrammability of fuse options using one-time programmable elements' [patent_app_type] => new [patent_app_number] => 09/882516 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4233 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035771.pdf [firstpage_image] =>[orig_patent_app_number] => 09882516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882516
Method and apparatus for limited reprogrammability of fuse options using one-time programmable elements Jun 14, 2001 Issued
Array ( [id] => 1424057 [patent_doc_number] => 06518795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Design simplicity of very high-speed semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/882977 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1921 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518795.pdf [firstpage_image] =>[orig_patent_app_number] => 09882977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882977
Design simplicity of very high-speed semiconductor device Jun 14, 2001 Issued
Menu