
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6933580
[patent_doc_number] => 20010054924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'Logic circuit having phase-controlled data receiving interface'
[patent_app_type] => new
[patent_app_number] => 09/810664
[patent_app_country] => US
[patent_app_date] => 2001-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9480
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20010054924.pdf
[firstpage_image] =>[orig_patent_app_number] => 09810664
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/810664 | Logic circuit having phase-controlled data receiving interface | Mar 18, 2001 | Issued |
Array
(
[id] => 5840955
[patent_doc_number] => 20020130686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'CMOS gate array with vertical transistors'
[patent_app_type] => new
[patent_app_number] => 09/808369
[patent_app_country] => US
[patent_app_date] => 2001-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7572
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20020130686.pdf
[firstpage_image] =>[orig_patent_app_number] => 09808369
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/808369 | CMOS gate array with vertical transistors | Mar 13, 2001 | Issued |
Array
(
[id] => 5871828
[patent_doc_number] => 20020047788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'High rate runlength limited codes for 10-bit ECC symbols'
[patent_app_type] => new
[patent_app_number] => 09/803401
[patent_app_country] => US
[patent_app_date] => 2001-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5425
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20020047788.pdf
[firstpage_image] =>[orig_patent_app_number] => 09803401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/803401 | High rate runlength limited codes for 10-bit ECC symbols | Mar 8, 2001 | Issued |
Array
(
[id] => 1441271
[patent_doc_number] => 06496036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-17
[patent_title] => 'Input-output buffer circuit'
[patent_app_type] => B2
[patent_app_number] => 09/801761
[patent_app_country] => US
[patent_app_date] => 2001-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6731
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/496/06496036.pdf
[firstpage_image] =>[orig_patent_app_number] => 09801761
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/801761 | Input-output buffer circuit | Mar 8, 2001 | Issued |
Array
(
[id] => 6948320
[patent_doc_number] => 20010021957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-13
[patent_title] => 'Signal transmission system'
[patent_app_type] => new
[patent_app_number] => 09/799961
[patent_app_country] => US
[patent_app_date] => 2001-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8210
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20010021957.pdf
[firstpage_image] =>[orig_patent_app_number] => 09799961
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/799961 | Signal transmission system | Mar 4, 2001 | Issued |
Array
(
[id] => 7026884
[patent_doc_number] => 20010013793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Programmable logic device incorporating function blocks operable as wide-shallow ram'
[patent_app_type] => new
[patent_app_number] => 09/798343
[patent_app_country] => US
[patent_app_date] => 2001-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6696
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20010013793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09798343
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/798343 | Programmable logic device incorporating function blocks operable as wide-shallow RAM | Feb 28, 2001 | Issued |
Array
(
[id] => 1226125
[patent_doc_number] => 06700401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Reduced noise line drivers and method of operation'
[patent_app_type] => B2
[patent_app_number] => 09/796660
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5958
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/700/06700401.pdf
[firstpage_image] =>[orig_patent_app_number] => 09796660
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/796660 | Reduced noise line drivers and method of operation | Feb 27, 2001 | Issued |
Array
(
[id] => 6893290
[patent_doc_number] => 20010015656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Buffer circuit'
[patent_app_type] => new
[patent_app_number] => 09/790050
[patent_app_country] => US
[patent_app_date] => 2001-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5577
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 376
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20010015656.pdf
[firstpage_image] =>[orig_patent_app_number] => 09790050
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790050 | Buffer circuit | Feb 20, 2001 | Issued |
Array
(
[id] => 6897678
[patent_doc_number] => 20010045843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-29
[patent_title] => 'Method and device for active impedance matching'
[patent_app_type] => new
[patent_app_number] => 09/790257
[patent_app_country] => US
[patent_app_date] => 2001-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6887
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20010045843.pdf
[firstpage_image] =>[orig_patent_app_number] => 09790257
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790257 | Method and device for active impedance matching | Feb 20, 2001 | Issued |
Array
(
[id] => 7026889
[patent_doc_number] => 20010013797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-16
[patent_title] => 'Logic cell and logic circuit using the same'
[patent_app_type] => new
[patent_app_number] => 09/771969
[patent_app_country] => US
[patent_app_date] => 2001-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 9305
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20010013797.pdf
[firstpage_image] =>[orig_patent_app_number] => 09771969
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/771969 | Logic cell and logic circuit using the same | Jan 29, 2001 | Issued |
Array
(
[id] => 7635899
[patent_doc_number] => 06380761
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Level converter provided with slew-rate controlling means'
[patent_app_type] => B1
[patent_app_number] => 09/744554
[patent_app_country] => US
[patent_app_date] => 2001-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3756
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/380/06380761.pdf
[firstpage_image] =>[orig_patent_app_number] => 09744554
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/744554 | Level converter provided with slew-rate controlling means | Jan 25, 2001 | Issued |
Array
(
[id] => 1211332
[patent_doc_number] => 06714052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-30
[patent_title] => 'Method and apparatus for passive component minimization of connector pins in a computer system'
[patent_app_type] => B2
[patent_app_number] => 09/770570
[patent_app_country] => US
[patent_app_date] => 2001-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2246
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/714/06714052.pdf
[firstpage_image] =>[orig_patent_app_number] => 09770570
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/770570 | Method and apparatus for passive component minimization of connector pins in a computer system | Jan 25, 2001 | Issued |
Array
(
[id] => 1497824
[patent_doc_number] => 06404223
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Self-terminating current mirror transceiver logic'
[patent_app_type] => B1
[patent_app_number] => 09/766758
[patent_app_country] => US
[patent_app_date] => 2001-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3868
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/404/06404223.pdf
[firstpage_image] =>[orig_patent_app_number] => 09766758
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/766758 | Self-terminating current mirror transceiver logic | Jan 21, 2001 | Issued |
Array
(
[id] => 5783497
[patent_doc_number] => 20020158663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Non-binary digital logic element and circuit design therefor'
[patent_app_type] => new
[patent_app_number] => 09/761662
[patent_app_country] => US
[patent_app_date] => 2001-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 15983
[patent_no_of_claims] => 77
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20020158663.pdf
[firstpage_image] =>[orig_patent_app_number] => 09761662
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/761662 | Non-binary digital logic element and circuit design therefor | Jan 17, 2001 | Abandoned |
Array
(
[id] => 1502800
[patent_doc_number] => 06486698
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'LSI device capable of adjusting the output impedance to match the characteristic impedance'
[patent_app_type] => B2
[patent_app_number] => 09/759160
[patent_app_country] => US
[patent_app_date] => 2001-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 6422
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/486/06486698.pdf
[firstpage_image] =>[orig_patent_app_number] => 09759160
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/759160 | LSI device capable of adjusting the output impedance to match the characteristic impedance | Jan 15, 2001 | Issued |
Array
(
[id] => 6417882
[patent_doc_number] => 20020125912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-12
[patent_title] => 'Tri-state buffer circuit'
[patent_app_type] => new
[patent_app_number] => 09/759354
[patent_app_country] => US
[patent_app_date] => 2001-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4359
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20020125912.pdf
[firstpage_image] =>[orig_patent_app_number] => 09759354
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/759354 | Tri-state buffer circuit | Jan 15, 2001 | Issued |
Array
(
[id] => 1370952
[patent_doc_number] => 06570401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-27
[patent_title] => 'Dual rail power supply sequence tolerant off-chip driver'
[patent_app_type] => B2
[patent_app_number] => 09/758054
[patent_app_country] => US
[patent_app_date] => 2001-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3424
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/570/06570401.pdf
[firstpage_image] =>[orig_patent_app_number] => 09758054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/758054 | Dual rail power supply sequence tolerant off-chip driver | Jan 9, 2001 | Issued |
Array
(
[id] => 1423089
[patent_doc_number] => 06522167
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'User configurable on-chip memory system'
[patent_app_type] => B1
[patent_app_number] => 09/757760
[patent_app_country] => US
[patent_app_date] => 2001-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5453
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/522/06522167.pdf
[firstpage_image] =>[orig_patent_app_number] => 09757760
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/757760 | User configurable on-chip memory system | Jan 8, 2001 | Issued |
Array
(
[id] => 1529974
[patent_doc_number] => 06480025
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Driver circuitry for programmable logic devices with hierarchical interconnection resources'
[patent_app_type] => B1
[patent_app_number] => 09/756461
[patent_app_country] => US
[patent_app_date] => 2001-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9298
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/480/06480025.pdf
[firstpage_image] =>[orig_patent_app_number] => 09756461
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/756461 | Driver circuitry for programmable logic devices with hierarchical interconnection resources | Jan 7, 2001 | Issued |
Array
(
[id] => 5965214
[patent_doc_number] => 20020089354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'Apparatus and method of providing a four input logic function'
[patent_app_type] => new
[patent_app_number] => 09/755854
[patent_app_country] => US
[patent_app_date] => 2001-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3369
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0089/20020089354.pdf
[firstpage_image] =>[orig_patent_app_number] => 09755854
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/755854 | Apparatus and method of providing a four input logic function | Jan 7, 2001 | Abandoned |