
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1406869
[patent_doc_number] => 06531894
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-11
[patent_title] => 'Pulse generation circuit and a drive circuit'
[patent_app_type] => B2
[patent_app_number] => 09/754062
[patent_app_country] => US
[patent_app_date] => 2001-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 18601
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[patent_words_short_claim] => 175
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531894.pdf
[firstpage_image] =>[orig_patent_app_number] => 09754062
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/754062 | Pulse generation circuit and a drive circuit | Jan 4, 2001 | Issued |
Array
(
[id] => 6638648
[patent_doc_number] => 20030006804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'CURRENT MODE LOGIC CIRCUIT WITH OUTPUT COMMON MODE VOLTAGE AND IMPEDANCE CONTROL'
[patent_app_type] => new
[patent_app_number] => 09/753268
[patent_app_country] => US
[patent_app_date] => 2000-12-29
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/753268 | Current mode logic circuit with output common mode voltage and impedance control | Dec 28, 2000 | Issued |
Array
(
[id] => 6902041
[patent_doc_number] => 20010000950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-10
[patent_title] => 'Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits'
[patent_app_type] => new-utility
[patent_app_number] => 09/751270
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751270 | Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits | Dec 28, 2000 | Issued |
Array
(
[id] => 1497875
[patent_doc_number] => 06404237
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Boosted multiplexer transmission gate'
[patent_app_type] => B1
[patent_app_number] => 09/752063
[patent_app_country] => US
[patent_app_date] => 2000-12-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/752063 | Boosted multiplexer transmission gate | Dec 28, 2000 | Issued |
Array
(
[id] => 1597747
[patent_doc_number] => 06384620
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[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Signal deciding apparatus'
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[patent_app_number] => 09/748852
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/748852 | Signal deciding apparatus | Dec 27, 2000 | Issued |
Array
(
[id] => 1394567
[patent_doc_number] => 06552569
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[patent_issue_date] => 2003-04-22
[patent_title] => 'Dual purpose low power input circuit for a memory device interface'
[patent_app_type] => B2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/745951 | Dual purpose low power input circuit for a memory device interface | Dec 21, 2000 | Issued |
Array
(
[id] => 1362957
[patent_doc_number] => 06577163
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Configurable PCI clamp or high voltage tolerant I/O circuit'
[patent_app_type] => B1
[patent_app_number] => 09/745658
[patent_app_country] => US
[patent_app_date] => 2000-12-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/745658 | Configurable PCI clamp or high voltage tolerant I/O circuit | Dec 20, 2000 | Issued |
Array
(
[id] => 1419363
[patent_doc_number] => 06529036
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-04
[patent_title] => 'Low noise, reduced swing differential output buffer design'
[patent_app_type] => B1
[patent_app_number] => 09/742758
[patent_app_country] => US
[patent_app_date] => 2000-12-20
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/742758 | Low noise, reduced swing differential output buffer design | Dec 19, 2000 | Issued |
Array
(
[id] => 6875561
[patent_doc_number] => 20010000654
[patent_country] => US
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[patent_issue_date] => 2001-05-03
[patent_title] => 'Low power, high speed level shifter'
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[patent_app_number] => 09/741368
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741368 | Low power, high speed level shifter | Dec 18, 2000 | Issued |
Array
(
[id] => 6124538
[patent_doc_number] => 20020075038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Active leakage control technique for high performance dynamic circuits'
[patent_app_type] => new
[patent_app_number] => 09/741367
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741367 | Active leakage control technique for high performance dynamic circuits | Dec 18, 2000 | Abandoned |
Array
(
[id] => 6895388
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[patent_title] => 'Output buffer circuit and control method therefor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/735555 | Output buffer circuit and control method therefor | Dec 13, 2000 | Issued |
Array
(
[id] => 1551275
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[patent_title] => 'Semiconductor integrated circuit having diagnosis function'
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Array
(
[id] => 6877311
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/729061 | 5V compliant transmission gate and the drive logic using 3.3V technology | Dec 3, 2000 | Issued |
Array
(
[id] => 1487287
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[patent_title] => 'Nonvolatile/battery-backed key in PLD'
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Array
(
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Array
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Array
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Array
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