Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1406869 [patent_doc_number] => 06531894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Pulse generation circuit and a drive circuit' [patent_app_type] => B2 [patent_app_number] => 09/754062 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 18601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531894.pdf [firstpage_image] =>[orig_patent_app_number] => 09754062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754062
Pulse generation circuit and a drive circuit Jan 4, 2001 Issued
Array ( [id] => 6638648 [patent_doc_number] => 20030006804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'CURRENT MODE LOGIC CIRCUIT WITH OUTPUT COMMON MODE VOLTAGE AND IMPEDANCE CONTROL' [patent_app_type] => new [patent_app_number] => 09/753268 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1909 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006804.pdf [firstpage_image] =>[orig_patent_app_number] => 09753268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753268
Current mode logic circuit with output common mode voltage and impedance control Dec 28, 2000 Issued
Array ( [id] => 6902041 [patent_doc_number] => 20010000950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits' [patent_app_type] => new-utility [patent_app_number] => 09/751270 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3841 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000950.pdf [firstpage_image] =>[orig_patent_app_number] => 09751270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751270
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits Dec 28, 2000 Issued
Array ( [id] => 1497875 [patent_doc_number] => 06404237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Boosted multiplexer transmission gate' [patent_app_type] => B1 [patent_app_number] => 09/752063 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404237.pdf [firstpage_image] =>[orig_patent_app_number] => 09752063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752063
Boosted multiplexer transmission gate Dec 28, 2000 Issued
Array ( [id] => 1597747 [patent_doc_number] => 06384620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Signal deciding apparatus' [patent_app_type] => B1 [patent_app_number] => 09/748852 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4911 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384620.pdf [firstpage_image] =>[orig_patent_app_number] => 09748852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748852
Signal deciding apparatus Dec 27, 2000 Issued
Array ( [id] => 1394567 [patent_doc_number] => 06552569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Dual purpose low power input circuit for a memory device interface' [patent_app_type] => B2 [patent_app_number] => 09/745951 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3193 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552569.pdf [firstpage_image] =>[orig_patent_app_number] => 09745951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745951
Dual purpose low power input circuit for a memory device interface Dec 21, 2000 Issued
Array ( [id] => 1362957 [patent_doc_number] => 06577163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Configurable PCI clamp or high voltage tolerant I/O circuit' [patent_app_type] => B1 [patent_app_number] => 09/745658 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3147 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/577/06577163.pdf [firstpage_image] =>[orig_patent_app_number] => 09745658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745658
Configurable PCI clamp or high voltage tolerant I/O circuit Dec 20, 2000 Issued
Array ( [id] => 1419363 [patent_doc_number] => 06529036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Low noise, reduced swing differential output buffer design' [patent_app_type] => B1 [patent_app_number] => 09/742758 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4303 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529036.pdf [firstpage_image] =>[orig_patent_app_number] => 09742758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742758
Low noise, reduced swing differential output buffer design Dec 19, 2000 Issued
Array ( [id] => 6875561 [patent_doc_number] => 20010000654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => new-utility [patent_app_number] => 09/741368 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2846 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000654.pdf [firstpage_image] =>[orig_patent_app_number] => 09741368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741368
Low power, high speed level shifter Dec 18, 2000 Issued
Array ( [id] => 6124538 [patent_doc_number] => 20020075038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Active leakage control technique for high performance dynamic circuits' [patent_app_type] => new [patent_app_number] => 09/741367 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4020 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075038.pdf [firstpage_image] =>[orig_patent_app_number] => 09741367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741367
Active leakage control technique for high performance dynamic circuits Dec 18, 2000 Abandoned
Array ( [id] => 6895388 [patent_doc_number] => 20010026178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Output buffer circuit and control method therefor' [patent_app_type] => new [patent_app_number] => 09/735555 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10167 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026178.pdf [firstpage_image] =>[orig_patent_app_number] => 09735555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735555
Output buffer circuit and control method therefor Dec 13, 2000 Issued
Array ( [id] => 1551275 [patent_doc_number] => 06346822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-12 [patent_title] => 'Semiconductor integrated circuit having diagnosis function' [patent_app_type] => B2 [patent_app_number] => 09/735757 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3163 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346822.pdf [firstpage_image] =>[orig_patent_app_number] => 09735757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735757
Semiconductor integrated circuit having diagnosis function Dec 12, 2000 Issued
Array ( [id] => 6877311 [patent_doc_number] => 20010002797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Logic gate' [patent_app_type] => new-utility [patent_app_number] => 09/729061 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002797.pdf [firstpage_image] =>[orig_patent_app_number] => 09729061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729061
5V compliant transmission gate and the drive logic using 3.3V technology Dec 3, 2000 Issued
Array ( [id] => 1487287 [patent_doc_number] => 06366117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Nonvolatile/battery-backed key in PLD' [patent_app_type] => B1 [patent_app_number] => 09/724973 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 13602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366117.pdf [firstpage_image] =>[orig_patent_app_number] => 09724973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724973
Nonvolatile/battery-backed key in PLD Nov 27, 2000 Issued
Array ( [id] => 1487265 [patent_doc_number] => 06366113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Data receiver' [patent_app_type] => B1 [patent_app_number] => 09/716557 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3876 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366113.pdf [firstpage_image] =>[orig_patent_app_number] => 09716557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716557
Data receiver Nov 19, 2000 Issued
Array ( [id] => 1436947 [patent_doc_number] => 06356107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method and structure dynamic in-system programming' [patent_app_type] => B1 [patent_app_number] => 09/712000 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356107.pdf [firstpage_image] =>[orig_patent_app_number] => 09712000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712000
Method and structure dynamic in-system programming Nov 12, 2000 Issued
Array ( [id] => 1563649 [patent_doc_number] => 06362648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Multiplexer for implementing logic functions in a programmable logic device' [patent_app_type] => B1 [patent_app_number] => 09/712038 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3856 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362648.pdf [firstpage_image] =>[orig_patent_app_number] => 09712038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712038
Multiplexer for implementing logic functions in a programmable logic device Nov 12, 2000 Issued
Array ( [id] => 4333779 [patent_doc_number] => 06329837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Termination circuits and methods therefor' [patent_app_type] => 1 [patent_app_number] => 9/705595 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 11970 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329837.pdf [firstpage_image] =>[orig_patent_app_number] => 705595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705595
Termination circuits and methods therefor Nov 1, 2000 Issued
Array ( [id] => 4280120 [patent_doc_number] => 06323675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Termination circuits and methods therefor' [patent_app_type] => 1 [patent_app_number] => 9/705425 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 11895 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323675.pdf [firstpage_image] =>[orig_patent_app_number] => 705425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705425
Termination circuits and methods therefor Nov 1, 2000 Issued
Array ( [id] => 4280134 [patent_doc_number] => 06323676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Termination circuits and methods therefor' [patent_app_type] => 1 [patent_app_number] => 9/706239 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 11906 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323676.pdf [firstpage_image] =>[orig_patent_app_number] => 706239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706239
Termination circuits and methods therefor Nov 1, 2000 Issued
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