Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7635901 [patent_doc_number] => 06380759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Variable grain architecture for FPGA integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/626094 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 51 [patent_no_of_words] => 52908 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380759.pdf [firstpage_image] =>[orig_patent_app_number] => 09626094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626094
Variable grain architecture for FPGA integrated circuits Jul 25, 2000 Issued
Array ( [id] => 1441258 [patent_doc_number] => 06496030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Scan flip-flop providing both scan and propagation delay testing' [patent_app_type] => B1 [patent_app_number] => 09/614257 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 12836 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496030.pdf [firstpage_image] =>[orig_patent_app_number] => 09614257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614257
Scan flip-flop providing both scan and propagation delay testing Jul 11, 2000 Issued
Array ( [id] => 1441280 [patent_doc_number] => 06496038 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Pulsed circuit topology including a pulsed, domino flip-flop' [patent_app_type] => B1 [patent_app_number] => 09/608857 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8179 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496038.pdf [firstpage_image] =>[orig_patent_app_number] => 09608857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608857
Pulsed circuit topology including a pulsed, domino flip-flop Jun 29, 2000 Issued
Array ( [id] => 1442253 [patent_doc_number] => 06335638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Triple-slope clock driver for reduced EMI' [patent_app_type] => B1 [patent_app_number] => 09/607558 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5794 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335638.pdf [firstpage_image] =>[orig_patent_app_number] => 09607558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607558
Triple-slope clock driver for reduced EMI Jun 28, 2000 Issued
Array ( [id] => 1425898 [patent_doc_number] => 06515507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Control pin for specifying integrated circuit voltage levels' [patent_app_type] => B1 [patent_app_number] => 09/607569 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4725 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515507.pdf [firstpage_image] =>[orig_patent_app_number] => 09607569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607569
Control pin for specifying integrated circuit voltage levels Jun 28, 2000 Issued
Array ( [id] => 4277443 [patent_doc_number] => 06307395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Termination circuits and methods for bused and networked devices' [patent_app_type] => 1 [patent_app_number] => 9/605919 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307395.pdf [firstpage_image] =>[orig_patent_app_number] => 605919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605919
Termination circuits and methods for bused and networked devices Jun 27, 2000 Issued
Array ( [id] => 1399161 [patent_doc_number] => 06549037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Apparatus and circuit having reduced leakage current and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/602667 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549037.pdf [firstpage_image] =>[orig_patent_app_number] => 09602667 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602667
Apparatus and circuit having reduced leakage current and method therefor Jun 25, 2000 Issued
Array ( [id] => 4361213 [patent_doc_number] => 06292017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Programmable logic device incorporating function blocks operable as wide-shallow RAM' [patent_app_type] => 1 [patent_app_number] => 9/603815 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292017.pdf [firstpage_image] =>[orig_patent_app_number] => 603815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603815
Programmable logic device incorporating function blocks operable as wide-shallow RAM Jun 25, 2000 Issued
Array ( [id] => 4414938 [patent_doc_number] => 06310493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/599646 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 21175 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310493.pdf [firstpage_image] =>[orig_patent_app_number] => 599646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599646
Semiconductor integrated circuit Jun 22, 2000 Issued
Array ( [id] => 1583588 [patent_doc_number] => 06424173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Voltage translators with zero static power and predictable performance' [patent_app_type] => B1 [patent_app_number] => 09/599058 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4114 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424173.pdf [firstpage_image] =>[orig_patent_app_number] => 09599058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599058
Voltage translators with zero static power and predictable performance Jun 20, 2000 Issued
Array ( [id] => 1448633 [patent_doc_number] => 06369616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Low power clock buffer with shared, precharge transistor' [patent_app_type] => B1 [patent_app_number] => 09/599050 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3585 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369616.pdf [firstpage_image] =>[orig_patent_app_number] => 09599050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599050
Low power clock buffer with shared, precharge transistor Jun 20, 2000 Issued
Array ( [id] => 4267872 [patent_doc_number] => 06259271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Configuration memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/595579 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4685 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259271.pdf [firstpage_image] =>[orig_patent_app_number] => 595579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595579
Configuration memory integrated circuit Jun 14, 2000 Issued
Array ( [id] => 1544851 [patent_doc_number] => 06373285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Level shift circuit' [patent_app_type] => B1 [patent_app_number] => 09/590260 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6265 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373285.pdf [firstpage_image] =>[orig_patent_app_number] => 09590260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590260
Level shift circuit Jun 8, 2000 Issued
Array ( [id] => 4294172 [patent_doc_number] => 06268746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method and apparatus for logic synchronization' [patent_app_type] => 1 [patent_app_number] => 9/586638 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 13025 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268746.pdf [firstpage_image] =>[orig_patent_app_number] => 586638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586638
Method and apparatus for logic synchronization Jun 4, 2000 Issued
Array ( [id] => 4387490 [patent_doc_number] => 06304101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device' [patent_app_type] => 1 [patent_app_number] => 9/585447 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 58 [patent_no_of_words] => 19117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304101.pdf [firstpage_image] =>[orig_patent_app_number] => 585447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585447
Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device Jun 1, 2000 Issued
Array ( [id] => 1472147 [patent_doc_number] => 06407575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Load insensitive clock source to enable hot swap of a node in a multiprocessor computer system' [patent_app_type] => B1 [patent_app_number] => 09/583965 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2404 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407575.pdf [firstpage_image] =>[orig_patent_app_number] => 09583965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583965
Load insensitive clock source to enable hot swap of a node in a multiprocessor computer system May 30, 2000 Issued
Array ( [id] => 1442230 [patent_doc_number] => 06335632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'CMOS small signal switchable terminator network' [patent_app_type] => B1 [patent_app_number] => 09/583055 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3729 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335632.pdf [firstpage_image] =>[orig_patent_app_number] => 09583055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583055
CMOS small signal switchable terminator network May 29, 2000 Issued
Array ( [id] => 4294102 [patent_doc_number] => 06268741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 9/573609 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 16256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268741.pdf [firstpage_image] =>[orig_patent_app_number] => 573609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573609
Semiconductor integrated circuits with power reduction mechanism May 18, 2000 Issued
Array ( [id] => 1535018 [patent_doc_number] => 06411121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Systems and methods for adjusting signal transmission parameters of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/571243 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411121.pdf [firstpage_image] =>[orig_patent_app_number] => 09571243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571243
Systems and methods for adjusting signal transmission parameters of an integrated circuit May 15, 2000 Issued
Array ( [id] => 4366851 [patent_doc_number] => 06191610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for implementing large multiplexers with FPGA lookup tables' [patent_app_type] => 1 [patent_app_number] => 9/570808 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 6976 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191610.pdf [firstpage_image] =>[orig_patent_app_number] => 570808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570808
Method for implementing large multiplexers with FPGA lookup tables May 14, 2000 Issued
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