
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4267131
[patent_doc_number] => 06204691
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'FPGA with a plurality of input reference voltage levels grouped into sets'
[patent_app_type] => 1
[patent_app_number] => 9/569745
[patent_app_country] => US
[patent_app_date] => 2000-05-11
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[patent_no_of_words] => 6050
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[pdf_file] => patents/06/204/06204691.pdf
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Array
(
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[patent_doc_number] => 06369609
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[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Degenerate network for PLD and plane'
[patent_app_type] => B1
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[firstpage_image] =>[orig_patent_app_number] => 09567455
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/567455 | Degenerate network for PLD and plane | May 7, 2000 | Issued |
Array
(
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[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Apparatus and method for interleaving a signal carry chain in an integrated circuit'
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[patent_app_number] => 09/565647
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/565647 | Apparatus and method for interleaving a signal carry chain in an integrated circuit | May 4, 2000 | Issued |
Array
(
[id] => 4361348
[patent_doc_number] => 06292026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Semiconductor device and electronic apparatus using the same'
[patent_app_type] => 1
[patent_app_number] => 9/565367
[patent_app_country] => US
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Array
(
[id] => 1419418
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[patent_title] => 'FPGA lookup table with speed read decoder'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09566052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566052 | FPGA lookup table with speed read decoder | May 4, 2000 | Issued |
Array
(
[id] => 4390010
[patent_doc_number] => 06278289
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[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Content-addressable memory implemented using programmable logic'
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[firstpage_image] =>[orig_patent_app_number] => 562646
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562646 | Content-addressable memory implemented using programmable logic | Apr 30, 2000 | Issued |
Array
(
[id] => 4267936
[patent_doc_number] => 06259275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Logic gate having reduced power dissipation and method of operation thereof'
[patent_app_type] => 1
[patent_app_number] => 9/562347
[patent_app_country] => US
[patent_app_date] => 2000-05-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/259/06259275.pdf
[firstpage_image] =>[orig_patent_app_number] => 562347
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562347 | Logic gate having reduced power dissipation and method of operation thereof | Apr 30, 2000 | Issued |
| 09/553739 | Programmable logic device incorporating function blocks operable as wide-shallow RAM | Apr 19, 2000 | Abandoned |
Array
(
[id] => 1419441
[patent_doc_number] => 06529042
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[patent_issue_date] => 2003-03-04
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/548658
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/548658 | Semiconductor integrated circuit | Apr 12, 2000 | Issued |
Array
(
[id] => 4333855
[patent_doc_number] => 06329842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Output circuit for electronic devices'
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[patent_app_number] => 9/547348
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/547348 | Output circuit for electronic devices | Apr 10, 2000 | Issued |
Array
(
[id] => 1462137
[patent_doc_number] => 06392444
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[patent_issue_date] => 2002-05-21
[patent_title] => 'IIL reset circuit'
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[patent_app_number] => 09/546660
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[firstpage_image] =>[orig_patent_app_number] => 09546660
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/546660 | IIL reset circuit | Apr 9, 2000 | Issued |
| 09/545566 | Buffer Circuit capable of carrying out interface with a high speed | Apr 6, 2000 | Abandoned |
Array
(
[id] => 1419321
[patent_doc_number] => 06529032
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[patent_title] => 'Methods and apparatus for full I/O functionality and blocking of backdrive current'
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Array
(
[id] => 4312054
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/539163 | FPGA-based communications access point and system for reconfiguration | Mar 28, 2000 | Issued |
Array
(
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[patent_title] => 'High speed, static digital multiplexer'
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Array
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Array
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Array
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Array
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Array
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