Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4267131 [patent_doc_number] => 06204691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'FPGA with a plurality of input reference voltage levels grouped into sets' [patent_app_type] => 1 [patent_app_number] => 9/569745 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204691.pdf [firstpage_image] =>[orig_patent_app_number] => 569745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569745
FPGA with a plurality of input reference voltage levels grouped into sets May 10, 2000 Issued
Array ( [id] => 1448608 [patent_doc_number] => 06369609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Degenerate network for PLD and plane' [patent_app_type] => B1 [patent_app_number] => 09/567455 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369609.pdf [firstpage_image] =>[orig_patent_app_number] => 09567455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567455
Degenerate network for PLD and plane May 7, 2000 Issued
Array ( [id] => 1497840 [patent_doc_number] => 06404227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Apparatus and method for interleaving a signal carry chain in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/565647 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2893 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404227.pdf [firstpage_image] =>[orig_patent_app_number] => 09565647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565647
Apparatus and method for interleaving a signal carry chain in an integrated circuit May 4, 2000 Issued
Array ( [id] => 4361348 [patent_doc_number] => 06292026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor device and electronic apparatus using the same' [patent_app_type] => 1 [patent_app_number] => 9/565367 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4542 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292026.pdf [firstpage_image] =>[orig_patent_app_number] => 565367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565367
Semiconductor device and electronic apparatus using the same May 4, 2000 Issued
Array ( [id] => 1419418 [patent_doc_number] => 06529040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'FPGA lookup table with speed read decoder' [patent_app_type] => B1 [patent_app_number] => 09/566052 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 10872 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529040.pdf [firstpage_image] =>[orig_patent_app_number] => 09566052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566052
FPGA lookup table with speed read decoder May 4, 2000 Issued
Array ( [id] => 4390010 [patent_doc_number] => 06278289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Content-addressable memory implemented using programmable logic' [patent_app_type] => 1 [patent_app_number] => 9/562646 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4784 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278289.pdf [firstpage_image] =>[orig_patent_app_number] => 562646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562646
Content-addressable memory implemented using programmable logic Apr 30, 2000 Issued
Array ( [id] => 4267936 [patent_doc_number] => 06259275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Logic gate having reduced power dissipation and method of operation thereof' [patent_app_type] => 1 [patent_app_number] => 9/562347 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8855 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259275.pdf [firstpage_image] =>[orig_patent_app_number] => 562347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562347
Logic gate having reduced power dissipation and method of operation thereof Apr 30, 2000 Issued
09/553739 Programmable logic device incorporating function blocks operable as wide-shallow RAM Apr 19, 2000 Abandoned
Array ( [id] => 1419441 [patent_doc_number] => 06529042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/548658 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3609 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529042.pdf [firstpage_image] =>[orig_patent_app_number] => 09548658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548658
Semiconductor integrated circuit Apr 12, 2000 Issued
Array ( [id] => 4333855 [patent_doc_number] => 06329842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Output circuit for electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/547348 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7084 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329842.pdf [firstpage_image] =>[orig_patent_app_number] => 547348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547348
Output circuit for electronic devices Apr 10, 2000 Issued
Array ( [id] => 1462137 [patent_doc_number] => 06392444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'IIL reset circuit' [patent_app_type] => B1 [patent_app_number] => 09/546660 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4216 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392444.pdf [firstpage_image] =>[orig_patent_app_number] => 09546660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546660
IIL reset circuit Apr 9, 2000 Issued
09/545566 Buffer Circuit capable of carrying out interface with a high speed Apr 6, 2000 Abandoned
Array ( [id] => 1419321 [patent_doc_number] => 06529032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Methods and apparatus for full I/O functionality and blocking of backdrive current' [patent_app_type] => B1 [patent_app_number] => 09/542267 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1108 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529032.pdf [firstpage_image] =>[orig_patent_app_number] => 09542267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542267
Methods and apparatus for full I/O functionality and blocking of backdrive current Apr 3, 2000 Issued
Array ( [id] => 4312054 [patent_doc_number] => 06326806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'FPGA-based communications access point and system for reconfiguration' [patent_app_type] => 1 [patent_app_number] => 9/539163 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4787 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326806.pdf [firstpage_image] =>[orig_patent_app_number] => 539163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539163
FPGA-based communications access point and system for reconfiguration Mar 28, 2000 Issued
Array ( [id] => 7629216 [patent_doc_number] => 06819141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'High speed, static digital multiplexer' [patent_app_type] => B1 [patent_app_number] => 09/524901 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3454 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819141.pdf [firstpage_image] =>[orig_patent_app_number] => 09524901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524901
High speed, static digital multiplexer Mar 13, 2000 Issued
Array ( [id] => 4414410 [patent_doc_number] => 06239618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Buffer with fast edge propagation' [patent_app_type] => 1 [patent_app_number] => 9/520057 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5226 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239618.pdf [firstpage_image] =>[orig_patent_app_number] => 520057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520057
Buffer with fast edge propagation Mar 6, 2000 Issued
Array ( [id] => 1554940 [patent_doc_number] => 06348814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Constant edge output buffer circuit and method' [patent_app_type] => B1 [patent_app_number] => 08/799953 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5539 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348814.pdf [firstpage_image] =>[orig_patent_app_number] => 08799953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799953
Constant edge output buffer circuit and method Feb 13, 2000 Issued
Array ( [id] => 4339156 [patent_doc_number] => 06313665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/402648 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12286 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313665.pdf [firstpage_image] =>[orig_patent_app_number] => 402648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/402648
Semiconductor integrated circuit Feb 2, 2000 Issued
Array ( [id] => 4160619 [patent_doc_number] => 06124731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Configurable logic element with ability to evaluate wide logic functions' [patent_app_type] => 1 [patent_app_number] => 9/480845 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4891 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124731.pdf [firstpage_image] =>[orig_patent_app_number] => 480845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480845
Configurable logic element with ability to evaluate wide logic functions Jan 9, 2000 Issued
Array ( [id] => 4277529 [patent_doc_number] => 06307401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Low voltage differential dual receiver' [patent_app_type] => 1 [patent_app_number] => 9/479464 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7481 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307401.pdf [firstpage_image] =>[orig_patent_app_number] => 479464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479464
Low voltage differential dual receiver Jan 5, 2000 Issued
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