Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1487692 [patent_doc_number] => 06366223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same' [patent_app_type] => B1 [patent_app_number] => 09/350097 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9218 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366223.pdf [firstpage_image] =>[orig_patent_app_number] => 09350097 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350097
Methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same Jul 8, 1999 Issued
Array ( [id] => 4088768 [patent_doc_number] => 06054873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Interconnect structure between heterogeneous core regions in a programmable array' [patent_app_type] => 1 [patent_app_number] => 9/338112 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6115 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054873.pdf [firstpage_image] =>[orig_patent_app_number] => 338112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338112
Interconnect structure between heterogeneous core regions in a programmable array Jun 22, 1999 Issued
Array ( [id] => 4149667 [patent_doc_number] => 06031391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Configuration memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/333144 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4693 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031391.pdf [firstpage_image] =>[orig_patent_app_number] => 333144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333144
Configuration memory integrated circuit Jun 13, 1999 Issued
Array ( [id] => 7630855 [patent_doc_number] => 06636077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'High isolation, low power high speed multiplexer circuit' [patent_app_type] => B1 [patent_app_number] => 09/330875 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3770 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636077.pdf [firstpage_image] =>[orig_patent_app_number] => 09330875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330875
High isolation, low power high speed multiplexer circuit Jun 10, 1999 Issued
Array ( [id] => 4267893 [patent_doc_number] => 06259272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Programmable logic array integrated circuit architectures' [patent_app_type] => 1 [patent_app_number] => 9/328704 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6048 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259272.pdf [firstpage_image] =>[orig_patent_app_number] => 328704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/328704
Programmable logic array integrated circuit architectures Jun 8, 1999 Issued
Array ( [id] => 4267103 [patent_doc_number] => 06204689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Input/output interconnect circuit for FPGAs' [patent_app_type] => 1 [patent_app_number] => 9/321513 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 22451 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204689.pdf [firstpage_image] =>[orig_patent_app_number] => 321513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321513
Input/output interconnect circuit for FPGAs May 26, 1999 Issued
Array ( [id] => 4375493 [patent_doc_number] => 06275062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Termination of transmission lines using simultaneously enabled pull-up and pull-down circuits' [patent_app_type] => 1 [patent_app_number] => 9/318544 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5441 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275062.pdf [firstpage_image] =>[orig_patent_app_number] => 318544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318544
Termination of transmission lines using simultaneously enabled pull-up and pull-down circuits May 24, 1999 Issued
Array ( [id] => 4303218 [patent_doc_number] => 06184700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Fail safe buffer capable of operating with a mixed voltage core' [patent_app_type] => 1 [patent_app_number] => 9/318158 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2979 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184700.pdf [firstpage_image] =>[orig_patent_app_number] => 318158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318158
Fail safe buffer capable of operating with a mixed voltage core May 24, 1999 Issued
Array ( [id] => 4280082 [patent_doc_number] => 06323672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Apparatus for reducing reflections when using dynamic termination logic signaling' [patent_app_type] => 1 [patent_app_number] => 9/315325 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4146 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323672.pdf [firstpage_image] =>[orig_patent_app_number] => 315325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315325
Apparatus for reducing reflections when using dynamic termination logic signaling May 18, 1999 Issued
Array ( [id] => 4280096 [patent_doc_number] => 06323673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Apparatus for dynamic termination logic signaling' [patent_app_type] => 1 [patent_app_number] => 9/315326 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4178 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323673.pdf [firstpage_image] =>[orig_patent_app_number] => 315326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315326
Apparatus for dynamic termination logic signaling May 18, 1999 Issued
Array ( [id] => 4115219 [patent_doc_number] => 06057709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Integrated XNOR flip-flop' [patent_app_type] => 1 [patent_app_number] => 9/313432 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057709.pdf [firstpage_image] =>[orig_patent_app_number] => 313432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313432
Integrated XNOR flip-flop May 16, 1999 Issued
Array ( [id] => 1448597 [patent_doc_number] => 06369604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Self-compensating output buffer' [patent_app_type] => B1 [patent_app_number] => 09/299254 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6409 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369604.pdf [firstpage_image] =>[orig_patent_app_number] => 09299254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299254
Self-compensating output buffer Apr 25, 1999 Issued
Array ( [id] => 4312267 [patent_doc_number] => 06252417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Fault identification by voltage potential signature' [patent_app_type] => 1 [patent_app_number] => 9/296336 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2973 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252417.pdf [firstpage_image] =>[orig_patent_app_number] => 296336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296336
Fault identification by voltage potential signature Apr 21, 1999 Issued
Array ( [id] => 4197136 [patent_doc_number] => 06154053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch' [patent_app_type] => 1 [patent_app_number] => 9/295735 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9335 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154053.pdf [firstpage_image] =>[orig_patent_app_number] => 295735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295735
Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch Apr 19, 1999 Issued
Array ( [id] => 4110287 [patent_doc_number] => 06051992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Configurable logic element with ability to evaluate five and six input functions' [patent_app_type] => 1 [patent_app_number] => 9/283472 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4897 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051992.pdf [firstpage_image] =>[orig_patent_app_number] => 283472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283472
Configurable logic element with ability to evaluate five and six input functions Mar 31, 1999 Issued
Array ( [id] => 4186549 [patent_doc_number] => 06037805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Integrated circuit device having small amplitude signal transmission' [patent_app_type] => 1 [patent_app_number] => 9/280726 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 12458 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037805.pdf [firstpage_image] =>[orig_patent_app_number] => 280726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280726
Integrated circuit device having small amplitude signal transmission Mar 28, 1999 Issued
Array ( [id] => 4256900 [patent_doc_number] => 06222388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Low voltage differential driver with multiple drive strengths' [patent_app_type] => 1 [patent_app_number] => 9/270947 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8109 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222388.pdf [firstpage_image] =>[orig_patent_app_number] => 270947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270947
Low voltage differential driver with multiple drive strengths Mar 16, 1999 Issued
09/255026 SEMI-HIERARCHICAL REPROGRAMMABLE FPGA ARCHITECTURE Feb 21, 1999 Abandoned
Array ( [id] => 4365134 [patent_doc_number] => 06169417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Product-term macrocells for programmable logic device' [patent_app_type] => 1 [patent_app_number] => 9/238101 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169417.pdf [firstpage_image] =>[orig_patent_app_number] => 238101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238101
Product-term macrocells for programmable logic device Jan 26, 1999 Issued
Array ( [id] => 4296279 [patent_doc_number] => 06211695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections' [patent_app_type] => 1 [patent_app_number] => 9/235615 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 25527 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211695.pdf [firstpage_image] =>[orig_patent_app_number] => 235615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235615
FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections Jan 20, 1999 Issued
Menu