Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4186449 [patent_doc_number] => 06037798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Line receiver circuit having termination impedances with transmission gates connected in parallel' [patent_app_type] => 1 [patent_app_number] => 9/186622 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4764 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037798.pdf [firstpage_image] =>[orig_patent_app_number] => 186622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186622
Line receiver circuit having termination impedances with transmission gates connected in parallel Nov 5, 1998 Issued
Array ( [id] => 4191630 [patent_doc_number] => 06150846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Bus circuit' [patent_app_type] => 1 [patent_app_number] => 9/187106 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6723 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150846.pdf [firstpage_image] =>[orig_patent_app_number] => 187106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187106
Bus circuit Nov 4, 1998 Issued
Array ( [id] => 4241349 [patent_doc_number] => 06118304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for logic synchronization' [patent_app_type] => 1 [patent_app_number] => 9/179330 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 13293 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118304.pdf [firstpage_image] =>[orig_patent_app_number] => 179330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179330
Method and apparatus for logic synchronization Oct 26, 1998 Issued
Array ( [id] => 4414365 [patent_doc_number] => 06239613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Tristate structures for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 9/169207 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7790 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239613.pdf [firstpage_image] =>[orig_patent_app_number] => 169207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169207
Tristate structures for programmable logic devices Oct 8, 1998 Issued
Array ( [id] => 4106331 [patent_doc_number] => 06066964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Dynamic bus' [patent_app_type] => 1 [patent_app_number] => 9/167032 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066964.pdf [firstpage_image] =>[orig_patent_app_number] => 167032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167032
Dynamic bus Oct 5, 1998 Issued
Array ( [id] => 4256829 [patent_doc_number] => 06222384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Level shifter circuit' [patent_app_type] => 1 [patent_app_number] => 9/166224 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 2767 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222384.pdf [firstpage_image] =>[orig_patent_app_number] => 166224 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166224
Level shifter circuit Oct 4, 1998 Issued
Array ( [id] => 4415775 [patent_doc_number] => 06265893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Signal line drivers' [patent_app_type] => 1 [patent_app_number] => 9/162801 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2826 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265893.pdf [firstpage_image] =>[orig_patent_app_number] => 162801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162801
Signal line drivers Sep 28, 1998 Issued
Array ( [id] => 4255586 [patent_doc_number] => 06137309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate' [patent_app_type] => 1 [patent_app_number] => 9/159316 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6722 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137309.pdf [firstpage_image] =>[orig_patent_app_number] => 159316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159316
Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate Sep 22, 1998 Issued
Array ( [id] => 4267205 [patent_doc_number] => 06204696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Domino circuits with high performance and high noise immunity' [patent_app_type] => 1 [patent_app_number] => 9/158410 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204696.pdf [firstpage_image] =>[orig_patent_app_number] => 158410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158410
Domino circuits with high performance and high noise immunity Sep 21, 1998 Issued
Array ( [id] => 4096968 [patent_doc_number] => 06133757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'High-speed and low-noise output buffer' [patent_app_type] => 1 [patent_app_number] => 9/156032 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4823 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133757.pdf [firstpage_image] =>[orig_patent_app_number] => 156032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156032
High-speed and low-noise output buffer Sep 16, 1998 Issued
Array ( [id] => 4028863 [patent_doc_number] => 05926036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Programmable logic array circuits comprising look up table implementation of fast carry adders and counters' [patent_app_type] => 1 [patent_app_number] => 9/136317 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 22051 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926036.pdf [firstpage_image] =>[orig_patent_app_number] => 136317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136317
Programmable logic array circuits comprising look up table implementation of fast carry adders and counters Aug 18, 1998 Issued
Array ( [id] => 4224333 [patent_doc_number] => 06111428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Programmable logic array' [patent_app_type] => 1 [patent_app_number] => 9/119625 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3285 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111428.pdf [firstpage_image] =>[orig_patent_app_number] => 119625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/119625
Programmable logic array Jul 20, 1998 Issued
Array ( [id] => 4296386 [patent_doc_number] => 06211701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Low power line switching circuit, device and method' [patent_app_type] => 1 [patent_app_number] => 9/111532 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 13008 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211701.pdf [firstpage_image] =>[orig_patent_app_number] => 111532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111532
Low power line switching circuit, device and method Jul 7, 1998 Issued
Array ( [id] => 4255701 [patent_doc_number] => 06137317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'CMOS driver' [patent_app_type] => 1 [patent_app_number] => 9/108606 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2295 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137317.pdf [firstpage_image] =>[orig_patent_app_number] => 108606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108606
CMOS driver Jun 30, 1998 Issued
Array ( [id] => 4164980 [patent_doc_number] => 06157215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method and apparatus for controlling impedance' [patent_app_type] => 1 [patent_app_number] => 9/106284 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3071 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157215.pdf [firstpage_image] =>[orig_patent_app_number] => 106284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106284
Method and apparatus for controlling impedance Jun 28, 1998 Issued
Array ( [id] => 4197826 [patent_doc_number] => 06130558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Data transfer circuit and method for a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/104152 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3909 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130558.pdf [firstpage_image] =>[orig_patent_app_number] => 104152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104152
Data transfer circuit and method for a semiconductor memory Jun 22, 1998 Issued
Array ( [id] => 4226167 [patent_doc_number] => 06040710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'CML-CMOS conversion circuit' [patent_app_type] => 1 [patent_app_number] => 9/092012 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5061 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040710.pdf [firstpage_image] =>[orig_patent_app_number] => 092012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092012
CML-CMOS conversion circuit Jun 3, 1998 Issued
Array ( [id] => 4197237 [patent_doc_number] => 06154060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Signaling circuit with substantially constant output impedance' [patent_app_type] => 1 [patent_app_number] => 9/089932 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2488 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154060.pdf [firstpage_image] =>[orig_patent_app_number] => 089932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089932
Signaling circuit with substantially constant output impedance Jun 2, 1998 Issued
Array ( [id] => 4088825 [patent_doc_number] => 06054877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Low power multiplexer circuit' [patent_app_type] => 1 [patent_app_number] => 9/090107 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1934 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054877.pdf [firstpage_image] =>[orig_patent_app_number] => 090107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090107
Low power multiplexer circuit Jun 2, 1998 Issued
Array ( [id] => 4224404 [patent_doc_number] => 06111433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Differential output driver with monotonic output transitions' [patent_app_type] => 1 [patent_app_number] => 9/089615 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111433.pdf [firstpage_image] =>[orig_patent_app_number] => 089615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089615
Differential output driver with monotonic output transitions Jun 2, 1998 Issued
Menu