
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3981989
[patent_doc_number] => 05905386
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments'
[patent_app_type] => 1
[patent_app_number] => 9/031715
[patent_app_country] => US
[patent_app_date] => 1998-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3598
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905386.pdf
[firstpage_image] =>[orig_patent_app_number] => 031715
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/031715 | CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments | Feb 26, 1998 | Issued |
Array
(
[id] => 4092710
[patent_doc_number] => 06018252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Dual-power type integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/011905
[patent_app_country] => US
[patent_app_date] => 1998-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2784
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018252.pdf
[firstpage_image] =>[orig_patent_app_number] => 011905
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/011905 | Dual-power type integrated circuit | Feb 22, 1998 | Issued |
Array
(
[id] => 4191578
[patent_doc_number] => 06150843
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Five volt tolerant I/O buffer'
[patent_app_type] => 1
[patent_app_number] => 9/015328
[patent_app_country] => US
[patent_app_date] => 1998-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3344
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/150/06150843.pdf
[firstpage_image] =>[orig_patent_app_number] => 015328
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/015328 | Five volt tolerant I/O buffer | Jan 28, 1998 | Issued |
Array
(
[id] => 4244790
[patent_doc_number] => 06144218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'High speed analog compensated input buffer'
[patent_app_type] => 1
[patent_app_number] => 9/012201
[patent_app_country] => US
[patent_app_date] => 1998-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3355
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144218.pdf
[firstpage_image] =>[orig_patent_app_number] => 012201
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/012201 | High speed analog compensated input buffer | Jan 22, 1998 | Issued |
Array
(
[id] => 4240765
[patent_doc_number] => 06075379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Slew rate control circuit'
[patent_app_type] => 1
[patent_app_number] => 9/012120
[patent_app_country] => US
[patent_app_date] => 1998-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4154
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/075/06075379.pdf
[firstpage_image] =>[orig_patent_app_number] => 012120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/012120 | Slew rate control circuit | Jan 21, 1998 | Issued |
Array
(
[id] => 4138948
[patent_doc_number] => 06034538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Virtual logic system for reconfigurable hardware'
[patent_app_type] => 1
[patent_app_number] => 9/010000
[patent_app_country] => US
[patent_app_date] => 1998-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4305
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034538.pdf
[firstpage_image] =>[orig_patent_app_number] => 010000
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010000 | Virtual logic system for reconfigurable hardware | Jan 20, 1998 | Issued |
Array
(
[id] => 4121816
[patent_doc_number] => 06046606
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Soft error protected dynamic circuit'
[patent_app_type] => 1
[patent_app_number] => 9/010200
[patent_app_country] => US
[patent_app_date] => 1998-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3165
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/046/06046606.pdf
[firstpage_image] =>[orig_patent_app_number] => 010200
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010200 | Soft error protected dynamic circuit | Jan 20, 1998 | Issued |
Array
(
[id] => 4240792
[patent_doc_number] => 06075381
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Programmable logic block in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/010335
[patent_app_country] => US
[patent_app_date] => 1998-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3521
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/075/06075381.pdf
[firstpage_image] =>[orig_patent_app_number] => 010335
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010335 | Programmable logic block in an integrated circuit | Jan 20, 1998 | Issued |
Array
(
[id] => 4326412
[patent_doc_number] => 06249143
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Programmable logic array integrated circuit with distributed random access memory array'
[patent_app_type] => 1
[patent_app_number] => 9/007718
[patent_app_country] => US
[patent_app_date] => 1998-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 7495
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/249/06249143.pdf
[firstpage_image] =>[orig_patent_app_number] => 007718
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/007718 | Programmable logic array integrated circuit with distributed random access memory array | Jan 14, 1998 | Issued |
Array
(
[id] => 3950303
[patent_doc_number] => 05982199
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance'
[patent_app_type] => 1
[patent_app_number] => 9/006209
[patent_app_country] => US
[patent_app_date] => 1998-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4016
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982199.pdf
[firstpage_image] =>[orig_patent_app_number] => 006209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/006209 | Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance | Jan 12, 1998 | Issued |
Array
(
[id] => 4149695
[patent_doc_number] => 06031393
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Pass gate input buffer for a mixed voltage environment'
[patent_app_type] => 1
[patent_app_number] => 9/001506
[patent_app_country] => US
[patent_app_date] => 1997-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3156
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/031/06031393.pdf
[firstpage_image] =>[orig_patent_app_number] => 001506
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/001506 | Pass gate input buffer for a mixed voltage environment | Dec 30, 1997 | Issued |
Array
(
[id] => 4182118
[patent_doc_number] => 06084430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Input buffer for a mixed voltage environment'
[patent_app_type] => 1
[patent_app_number] => 9/002232
[patent_app_country] => US
[patent_app_date] => 1997-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3688
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/084/06084430.pdf
[firstpage_image] =>[orig_patent_app_number] => 002232
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002232 | Input buffer for a mixed voltage environment | Dec 30, 1997 | Issued |
Array
(
[id] => 4213984
[patent_doc_number] => 06028445
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Decoder structure and method for FPGA configuration'
[patent_app_type] => 1
[patent_app_number] => 9/000519
[patent_app_country] => US
[patent_app_date] => 1997-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6161
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/028/06028445.pdf
[firstpage_image] =>[orig_patent_app_number] => 000519
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/000519 | Decoder structure and method for FPGA configuration | Dec 29, 1997 | Issued |
Array
(
[id] => 4040556
[patent_doc_number] => 05942917
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'High speed ratioed CMOS logic structures for a pulsed input environment'
[patent_app_type] => 1
[patent_app_number] => 8/999102
[patent_app_country] => US
[patent_app_date] => 1997-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4243
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/942/05942917.pdf
[firstpage_image] =>[orig_patent_app_number] => 999102
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999102 | High speed ratioed CMOS logic structures for a pulsed input environment | Dec 28, 1997 | Issued |
| 08/998414 | AMPLIFIER FOR ACTIVE TERMINATOR | Dec 23, 1997 | Abandoned |
Array
(
[id] => 4182054
[patent_doc_number] => 06084426
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Compensated input receiver with controlled switch-point'
[patent_app_type] => 1
[patent_app_number] => 8/998293
[patent_app_country] => US
[patent_app_date] => 1997-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3877
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/084/06084426.pdf
[firstpage_image] =>[orig_patent_app_number] => 998293
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/998293 | Compensated input receiver with controlled switch-point | Dec 23, 1997 | Issued |
Array
(
[id] => 4199614
[patent_doc_number] => 06043682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Predriver logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/997223
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4872
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/043/06043682.pdf
[firstpage_image] =>[orig_patent_app_number] => 997223
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997223 | Predriver logic circuit | Dec 22, 1997 | Issued |
Array
(
[id] => 4139041
[patent_doc_number] => 06034544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Programmable input/output block (IOB) in FPGA integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/995615
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 58
[patent_no_of_words] => 31590
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034544.pdf
[firstpage_image] =>[orig_patent_app_number] => 995615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995615 | Programmable input/output block (IOB) in FPGA integrated circuits | Dec 21, 1997 | Issued |
Array
(
[id] => 4163647
[patent_doc_number] => 06107823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/997221
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 58
[patent_no_of_words] => 31658
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/107/06107823.pdf
[firstpage_image] =>[orig_patent_app_number] => 997221
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997221 | Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits | Dec 21, 1997 | Issued |
Array
(
[id] => 3950193
[patent_doc_number] => 05982193
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/995614
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 58
[patent_no_of_words] => 31439
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982193.pdf
[firstpage_image] =>[orig_patent_app_number] => 995614
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995614 | Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits | Dec 21, 1997 | Issued |