Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3955554 [patent_doc_number] => 05999015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Logic region resources for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/902416 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6897 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999015.pdf [firstpage_image] =>[orig_patent_app_number] => 902416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902416
Logic region resources for programmable logic devices Jul 28, 1997 Issued
Array ( [id] => 4214012 [patent_doc_number] => 06028447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'FPGA having predictable open-drain drive mode' [patent_app_type] => 1 [patent_app_number] => 8/899428 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2078 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028447.pdf [firstpage_image] =>[orig_patent_app_number] => 899428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899428
FPGA having predictable open-drain drive mode Jul 23, 1997 Issued
Array ( [id] => 4357894 [patent_doc_number] => 06215329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Output stage for a memory device and for low voltage applications' [patent_app_type] => 1 [patent_app_number] => 8/899228 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7002 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215329.pdf [firstpage_image] =>[orig_patent_app_number] => 899228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899228
Output stage for a memory device and for low voltage applications Jul 22, 1997 Issued
Array ( [id] => 4011606 [patent_doc_number] => 06005415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Switching circuit for large voltages' [patent_app_type] => 1 [patent_app_number] => 8/896924 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2199 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005415.pdf [firstpage_image] =>[orig_patent_app_number] => 896924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896924
Switching circuit for large voltages Jul 17, 1997 Issued
Array ( [id] => 4149629 [patent_doc_number] => 06031388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Postcharged interconnection speed-up circuit' [patent_app_type] => 1 [patent_app_number] => 8/896614 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031388.pdf [firstpage_image] =>[orig_patent_app_number] => 896614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896614
Postcharged interconnection speed-up circuit Jul 17, 1997 Issued
Array ( [id] => 4103902 [patent_doc_number] => 06097211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Configuration memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/893231 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4693 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097211.pdf [firstpage_image] =>[orig_patent_app_number] => 893231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893231
Configuration memory integrated circuit Jul 14, 1997 Issued
Array ( [id] => 4226232 [patent_doc_number] => 06040715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Output buffer control circuit that performs high speed operation by generating a predetermined width of a pulse based on an output control signal' [patent_app_type] => 1 [patent_app_number] => 8/893613 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4512 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040715.pdf [firstpage_image] =>[orig_patent_app_number] => 893613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893613
Output buffer control circuit that performs high speed operation by generating a predetermined width of a pulse based on an output control signal Jul 10, 1997 Issued
Array ( [id] => 3942745 [patent_doc_number] => 05929654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Temperature-insensitive current controlled CMOS output driver' [patent_app_type] => 1 [patent_app_number] => 8/891153 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3102 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929654.pdf [firstpage_image] =>[orig_patent_app_number] => 891153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891153
Temperature-insensitive current controlled CMOS output driver Jul 9, 1997 Issued
Array ( [id] => 4028875 [patent_doc_number] => 05926037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Buffer circuit which transfers data held in a first latch circuit to a second latch circuit' [patent_app_type] => 1 [patent_app_number] => 8/890619 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8379 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926037.pdf [firstpage_image] =>[orig_patent_app_number] => 890619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890619
Buffer circuit which transfers data held in a first latch circuit to a second latch circuit Jul 8, 1997 Issued
Array ( [id] => 4199518 [patent_doc_number] => 06043675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Logic circuit utilizing capacitive coupling, an AD converter and a DA converter' [patent_app_type] => 1 [patent_app_number] => 8/888900 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 84 [patent_no_of_words] => 20286 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043675.pdf [firstpage_image] =>[orig_patent_app_number] => 888900 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888900
Logic circuit utilizing capacitive coupling, an AD converter and a DA converter Jul 6, 1997 Issued
Array ( [id] => 3955583 [patent_doc_number] => 05999017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'CMOS implemented output buffer circuit for providing ECL level signals' [patent_app_type] => 1 [patent_app_number] => 8/887827 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2330 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999017.pdf [firstpage_image] =>[orig_patent_app_number] => 887827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887827
CMOS implemented output buffer circuit for providing ECL level signals Jul 2, 1997 Issued
Array ( [id] => 4088780 [patent_doc_number] => 06054874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Output driver circuit with switched current source' [patent_app_type] => 1 [patent_app_number] => 8/886914 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4899 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054874.pdf [firstpage_image] =>[orig_patent_app_number] => 886914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886914
Output driver circuit with switched current source Jul 1, 1997 Issued
Array ( [id] => 3952826 [patent_doc_number] => 05990701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of broadly distributing termination for buses using switched terminators' [patent_app_type] => 1 [patent_app_number] => 8/881927 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2115 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990701.pdf [firstpage_image] =>[orig_patent_app_number] => 881927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881927
Method of broadly distributing termination for buses using switched terminators Jun 24, 1997 Issued
Array ( [id] => 4092420 [patent_doc_number] => 06025736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Fast reprogrammable logic with active links between cells' [patent_app_type] => 1 [patent_app_number] => 8/869201 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 14868 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025736.pdf [firstpage_image] =>[orig_patent_app_number] => 869201 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869201
Fast reprogrammable logic with active links between cells Jun 3, 1997 Issued
Array ( [id] => 4000621 [patent_doc_number] => 05920205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Loading element for a logic gate' [patent_app_type] => 1 [patent_app_number] => 8/866756 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 1771 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920205.pdf [firstpage_image] =>[orig_patent_app_number] => 866756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866756
Loading element for a logic gate May 29, 1997 Issued
Array ( [id] => 3942773 [patent_doc_number] => 05929656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and apparatus for driving a capacitive display device' [patent_app_type] => 1 [patent_app_number] => 8/857778 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6200 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929656.pdf [firstpage_image] =>[orig_patent_app_number] => 857778 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857778
Method and apparatus for driving a capacitive display device May 15, 1997 Issued
Array ( [id] => 4091282 [patent_doc_number] => 06163170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Level converter and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/857269 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163170.pdf [firstpage_image] =>[orig_patent_app_number] => 857269 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857269
Level converter and semiconductor device May 15, 1997 Issued
Array ( [id] => 3956740 [patent_doc_number] => 05977793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Programmable logic device with hierarchical interconnection resources' [patent_app_type] => 1 [patent_app_number] => 8/855192 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8011 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977793.pdf [firstpage_image] =>[orig_patent_app_number] => 855192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/855192
Programmable logic device with hierarchical interconnection resources May 12, 1997 Issued
Array ( [id] => 3910824 [patent_doc_number] => 05898319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method and structure for providing fast conditional sum in a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/853975 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6519 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898319.pdf [firstpage_image] =>[orig_patent_app_number] => 853975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853975
Method and structure for providing fast conditional sum in a field programmable gate array May 8, 1997 Issued
Array ( [id] => 4030297 [patent_doc_number] => 05926136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Antenna apparatus' [patent_app_type] => 1 [patent_app_number] => 8/852599 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6942 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926136.pdf [firstpage_image] =>[orig_patent_app_number] => 852599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852599
Antenna apparatus May 6, 1997 Issued
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