Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3946408 [patent_doc_number] => 05973513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Integrated circuit arrangement with an open-collector transistor designed as npn transistor' [patent_app_type] => 1 [patent_app_number] => 8/852473 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3850 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973513.pdf [firstpage_image] =>[orig_patent_app_number] => 852473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852473
Integrated circuit arrangement with an open-collector transistor designed as npn transistor May 6, 1997 Issued
Array ( [id] => 3974710 [patent_doc_number] => 05886537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells' [patent_app_type] => 1 [patent_app_number] => 8/850472 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 6893 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886537.pdf [firstpage_image] =>[orig_patent_app_number] => 850472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850472
Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells May 4, 1997 Issued
Array ( [id] => 4005327 [patent_doc_number] => 05986479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Fully switched, class-B, high speed current amplifier driver' [patent_app_type] => 1 [patent_app_number] => 8/841813 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8195 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986479.pdf [firstpage_image] =>[orig_patent_app_number] => 841813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841813
Fully switched, class-B, high speed current amplifier driver May 4, 1997 Issued
Array ( [id] => 3803716 [patent_doc_number] => 05828229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/847004 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 18914 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828229.pdf [firstpage_image] =>[orig_patent_app_number] => 847004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847004
Programmable logic array integrated circuits Apr 30, 1997 Issued
Array ( [id] => 4015065 [patent_doc_number] => 05889414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Programmable circuits' [patent_app_type] => 1 [patent_app_number] => 8/840337 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2443 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889414.pdf [firstpage_image] =>[orig_patent_app_number] => 840337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840337
Programmable circuits Apr 27, 1997 Issued
Array ( [id] => 4050002 [patent_doc_number] => 05874837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'CMOS PECL driver with programmable current for varying voltage swings and termination types' [patent_app_type] => 1 [patent_app_number] => 8/847819 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5709 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874837.pdf [firstpage_image] =>[orig_patent_app_number] => 847819 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847819
CMOS PECL driver with programmable current for varying voltage swings and termination types Apr 27, 1997 Issued
Array ( [id] => 4059080 [patent_doc_number] => 05933029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit' [patent_app_type] => 1 [patent_app_number] => 8/848126 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 12458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933029.pdf [firstpage_image] =>[orig_patent_app_number] => 848126 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848126
Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit Apr 27, 1997 Issued
Array ( [id] => 3941004 [patent_doc_number] => 05939899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'MOSFET substrate current logic' [patent_app_type] => 1 [patent_app_number] => 8/842123 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2847 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939899.pdf [firstpage_image] =>[orig_patent_app_number] => 842123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842123
MOSFET substrate current logic Apr 22, 1997 Issued
Array ( [id] => 3982296 [patent_doc_number] => 05917335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Output voltage controlled impedance output buffer' [patent_app_type] => 1 [patent_app_number] => 8/837782 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3230 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917335.pdf [firstpage_image] =>[orig_patent_app_number] => 837782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837782
Output voltage controlled impedance output buffer Apr 21, 1997 Issued
Array ( [id] => 3950252 [patent_doc_number] => 05982196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Programmable logic device producing a complementary bit line signal' [patent_app_type] => 1 [patent_app_number] => 8/847739 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4025 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982196.pdf [firstpage_image] =>[orig_patent_app_number] => 847739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847739
Programmable logic device producing a complementary bit line signal Apr 21, 1997 Issued
Array ( [id] => 4032370 [patent_doc_number] => 05883526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Hierarchical interconnect for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/840113 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883526.pdf [firstpage_image] =>[orig_patent_app_number] => 840113 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840113
Hierarchical interconnect for programmable logic devices Apr 16, 1997 Issued
Array ( [id] => 4032411 [patent_doc_number] => 05883529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same' [patent_app_type] => 1 [patent_app_number] => 8/834146 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 36 [patent_no_of_words] => 11269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883529.pdf [firstpage_image] =>[orig_patent_app_number] => 834146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834146
Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same Apr 13, 1997 Issued
Array ( [id] => 3974736 [patent_doc_number] => 05886539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Communication within an integrated circuit by data serialization through a metal plane' [patent_app_type] => 1 [patent_app_number] => 8/835935 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2778 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886539.pdf [firstpage_image] =>[orig_patent_app_number] => 835935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835935
Communication within an integrated circuit by data serialization through a metal plane Apr 9, 1997 Issued
Array ( [id] => 3986883 [patent_doc_number] => 05949249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Driver having inductance-controlled current slew rate' [patent_app_type] => 1 [patent_app_number] => 8/838572 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4016 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949249.pdf [firstpage_image] =>[orig_patent_app_number] => 838572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838572
Driver having inductance-controlled current slew rate Apr 9, 1997 Issued
Array ( [id] => 4000579 [patent_doc_number] => 05920202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Configurable logic element with ability to evaluate five and six input functions' [patent_app_type] => 1 [patent_app_number] => 8/835088 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4939 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920202.pdf [firstpage_image] =>[orig_patent_app_number] => 835088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835088
Configurable logic element with ability to evaluate five and six input functions Apr 3, 1997 Issued
Array ( [id] => 4205024 [patent_doc_number] => 06014038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Function block architecture for gate array' [patent_app_type] => 1 [patent_app_number] => 8/821475 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 9660 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014038.pdf [firstpage_image] =>[orig_patent_app_number] => 821475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821475
Function block architecture for gate array Mar 20, 1997 Issued
Array ( [id] => 4163658 [patent_doc_number] => 06104210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method for avoiding bus contention in a digital circuit' [patent_app_type] => 1 [patent_app_number] => 8/807298 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104210.pdf [firstpage_image] =>[orig_patent_app_number] => 807298 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807298
Method for avoiding bus contention in a digital circuit Feb 26, 1997 Issued
Array ( [id] => 3928293 [patent_doc_number] => 05914616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'FPGA repeatable interconnect structure with hierarchical interconnect lines' [patent_app_type] => 1 [patent_app_number] => 8/806997 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13583 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914616.pdf [firstpage_image] =>[orig_patent_app_number] => 806997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806997
FPGA repeatable interconnect structure with hierarchical interconnect lines Feb 25, 1997 Issued
Array ( [id] => 3943079 [patent_doc_number] => 05940043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Unidirectional field antenna for identification system' [patent_app_type] => 1 [patent_app_number] => 8/804193 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1916 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940043.pdf [firstpage_image] =>[orig_patent_app_number] => 804193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804193
Unidirectional field antenna for identification system Feb 20, 1997 Issued
Array ( [id] => 3954962 [patent_doc_number] => 05990848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Combined structure of a helical antenna and a dielectric plate' [patent_app_type] => 1 [patent_app_number] => 8/801884 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 2561 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990848.pdf [firstpage_image] =>[orig_patent_app_number] => 801884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801884
Combined structure of a helical antenna and a dielectric plate Feb 17, 1997 Issued
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