
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3847271
[patent_doc_number] => 05847581
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Low power CMOS precision input receiver with integrated reference'
[patent_app_type] => 1
[patent_app_number] => 8/775785
[patent_app_country] => US
[patent_app_date] => 1996-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3749
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847581.pdf
[firstpage_image] =>[orig_patent_app_number] => 775785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775785 | Low power CMOS precision input receiver with integrated reference | Dec 30, 1996 | Issued |
Array
(
[id] => 3941018
[patent_doc_number] => 05939900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Input buffer'
[patent_app_type] => 1
[patent_app_number] => 8/775290
[patent_app_country] => US
[patent_app_date] => 1996-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2976
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/939/05939900.pdf
[firstpage_image] =>[orig_patent_app_number] => 775290
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775290 | Input buffer | Dec 30, 1996 | Issued |
Array
(
[id] => 3965856
[patent_doc_number] => 05900744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method and apparatus for providing a high speed tristate buffer'
[patent_app_type] => 1
[patent_app_number] => 8/774431
[patent_app_country] => US
[patent_app_date] => 1996-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4054
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/900/05900744.pdf
[firstpage_image] =>[orig_patent_app_number] => 774431
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/774431 | Method and apparatus for providing a high speed tristate buffer | Dec 29, 1996 | Issued |
Array
(
[id] => 4011537
[patent_doc_number] => 06005411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type'
[patent_app_type] => 1
[patent_app_number] => 8/777296
[patent_app_country] => US
[patent_app_date] => 1996-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1486
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/005/06005411.pdf
[firstpage_image] =>[orig_patent_app_number] => 777296
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777296 | Monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type | Dec 26, 1996 | Issued |
| 08/773689 | SINGLE-PHASE DOMINO TIME BORROWING LOGIC WITH CLOCKS AT FIRST AND LASTSTAGES AND LATCH AT LAST STAGE | Dec 26, 1996 | Abandoned |
Array
(
[id] => 4256815
[patent_doc_number] => 06222383
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Controlled PMOS load on a CMOS PLA'
[patent_app_type] => 1
[patent_app_number] => 8/773136
[patent_app_country] => US
[patent_app_date] => 1996-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2897
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 426
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/222/06222383.pdf
[firstpage_image] =>[orig_patent_app_number] => 773136
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/773136 | Controlled PMOS load on a CMOS PLA | Dec 25, 1996 | Issued |
Array
(
[id] => 4092406
[patent_doc_number] => 06025735
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Programmable switch matrix and method of programming'
[patent_app_type] => 1
[patent_app_number] => 8/772735
[patent_app_country] => US
[patent_app_date] => 1996-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4039
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025735.pdf
[firstpage_image] =>[orig_patent_app_number] => 772735
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772735 | Programmable switch matrix and method of programming | Dec 22, 1996 | Issued |
Array
(
[id] => 3910798
[patent_doc_number] => 05898317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Configurable monolithic semiconductor circuit and method for configuring'
[patent_app_type] => 1
[patent_app_number] => 8/772736
[patent_app_country] => US
[patent_app_date] => 1996-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2432
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/898/05898317.pdf
[firstpage_image] =>[orig_patent_app_number] => 772736
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772736 | Configurable monolithic semiconductor circuit and method for configuring | Dec 22, 1996 | Issued |
Array
(
[id] => 4004501
[patent_doc_number] => 05923184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Ferroelectric transistor logic functions for programming'
[patent_app_type] => 1
[patent_app_number] => 8/772744
[patent_app_country] => US
[patent_app_date] => 1996-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 7395
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923184.pdf
[firstpage_image] =>[orig_patent_app_number] => 772744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772744 | Ferroelectric transistor logic functions for programming | Dec 22, 1996 | Issued |
Array
(
[id] => 4071569
[patent_doc_number] => 05867038
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Self-timed low power ratio-logic system having an input sensing circuit'
[patent_app_type] => 1
[patent_app_number] => 8/777689
[patent_app_country] => US
[patent_app_date] => 1996-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2333
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/867/05867038.pdf
[firstpage_image] =>[orig_patent_app_number] => 777689
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777689 | Self-timed low power ratio-logic system having an input sensing circuit | Dec 19, 1996 | Issued |
Array
(
[id] => 3956541
[patent_doc_number] => 05955893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Power saving buffer circuit buffer bias voltages'
[patent_app_type] => 1
[patent_app_number] => 8/767447
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 10176
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/955/05955893.pdf
[firstpage_image] =>[orig_patent_app_number] => 767447
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767447 | Power saving buffer circuit buffer bias voltages | Dec 15, 1996 | Issued |
| 08/767193 | LOW POWER BUS DRIVING CIRCUIT, DEVICE AND METHOD | Dec 15, 1996 | Abandoned |
Array
(
[id] => 3963038
[patent_doc_number] => 05936423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Semiconductor IC with an output circuit power supply used as a signal input/output terminal'
[patent_app_type] => 1
[patent_app_number] => 8/766341
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 5697
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/936/05936423.pdf
[firstpage_image] =>[orig_patent_app_number] => 766341
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766341 | Semiconductor IC with an output circuit power supply used as a signal input/output terminal | Dec 15, 1996 | Issued |
Array
(
[id] => 3991073
[patent_doc_number] => 05910730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Digital circuit noise margin improvement'
[patent_app_type] => 1
[patent_app_number] => 8/764951
[patent_app_country] => US
[patent_app_date] => 1996-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6236
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/910/05910730.pdf
[firstpage_image] =>[orig_patent_app_number] => 764951
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764951 | Digital circuit noise margin improvement | Dec 12, 1996 | Issued |
Array
(
[id] => 4414420
[patent_doc_number] => 06239619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Method and apparatus for dynamic termination logic of data buses'
[patent_app_type] => 1
[patent_app_number] => 8/763687
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/239/06239619.pdf
[firstpage_image] =>[orig_patent_app_number] => 763687
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763687 | Method and apparatus for dynamic termination logic of data buses | Dec 10, 1996 | Issued |
Array
(
[id] => 4021279
[patent_doc_number] => 05880599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'On/off control for a balanced differential current mode driver'
[patent_app_type] => 1
[patent_app_number] => 8/764547
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6433
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/880/05880599.pdf
[firstpage_image] =>[orig_patent_app_number] => 764547
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764547 | On/off control for a balanced differential current mode driver | Dec 10, 1996 | Issued |
Array
(
[id] => 4205049
[patent_doc_number] => 06014040
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'Bi-directional signal transmission system'
[patent_app_type] => 1
[patent_app_number] => 8/767597
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 5472
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/014/06014040.pdf
[firstpage_image] =>[orig_patent_app_number] => 767597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767597 | Bi-directional signal transmission system | Dec 8, 1996 | Issued |
Array
(
[id] => 4011522
[patent_doc_number] => 06005410
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Interconnect structure between heterogeneous core regions in a programmable array'
[patent_app_type] => 1
[patent_app_number] => 8/761037
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6074
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 397
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/005/06005410.pdf
[firstpage_image] =>[orig_patent_app_number] => 761037
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761037 | Interconnect structure between heterogeneous core regions in a programmable array | Dec 4, 1996 | Issued |
Array
(
[id] => 3776819
[patent_doc_number] => 05850155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip'
[patent_app_type] => 1
[patent_app_number] => 8/758664
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2980
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850155.pdf
[firstpage_image] =>[orig_patent_app_number] => 758664
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758664 | BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip | Dec 1, 1996 | Issued |
Array
(
[id] => 3847197
[patent_doc_number] => 05847576
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Low power, variable logic threshold voltage, logic gates'
[patent_app_type] => 1
[patent_app_number] => 8/746261
[patent_app_country] => US
[patent_app_date] => 1996-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2221
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847576.pdf
[firstpage_image] =>[orig_patent_app_number] => 746261
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746261 | Low power, variable logic threshold voltage, logic gates | Nov 6, 1996 | Issued |