Daniel D. Chang

Array ( [id] => 11961129 [patent_doc_number] => 20170265282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'LIGHT SOURCE CONTROL SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/411980 [patent_app_country] => US [patent_app_date] => 2017-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8981 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14394369 [patent_doc_number] => 10310464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Smart devices kit for recessed light housing [patent_app_type] => utility [patent_app_number] => 15/411994 [patent_app_country] => US [patent_app_date] => 2017-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 3367 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11617930 [patent_doc_number] => 20170128117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'WEARABLE COLD PLASMA SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/411407 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12339945 [patent_doc_number] => 09949328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Constant voltage output AC phase dimmable LED driver [patent_app_type] => utility [patent_app_number] => 15/410186 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11760185 [patent_doc_number] => 20170207054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'ION SOURCE CATHODE SHIELD' [patent_app_type] => utility [patent_app_number] => 15/410711 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11623817 [patent_doc_number] => 20170134006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'IMPEDANCE CALIBRATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/409057 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4601 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12063414 [patent_doc_number] => 20170339758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'TWO-TERMINAL INTEGRATED CIRCUITS WITH TIME-VARYING VOLTAGE-CURRENT CHARACTERISTICS INCLUDING PHASED-LOCKED POWER SUPPLIES' [patent_app_type] => utility [patent_app_number] => 15/406293 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 26239 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13570565 [patent_doc_number] => 20180336830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => ARRAY SUBSTRATES FOR ENHANCING GATE DRIVER ON ARRAY (GOA) RELIABILITY [patent_app_type] => utility [patent_app_number] => 15/328476 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15328476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11623651 [patent_doc_number] => 20170133839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'STRUCTURE AND METHOD FOR DYNAMIC BIASING TO IMPROVE ESD ROBUSTNESS OF CURRENT MODE LOGIC (CML) DRIVERS' [patent_app_type] => utility [patent_app_number] => 15/398871 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12055132 [patent_doc_number] => 20170331476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'IMPEDANCE CALIBRATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/390851 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12970741 [patent_doc_number] => 09876503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Method of obfuscating digital logic circuits using threshold voltage [patent_app_type] => utility [patent_app_number] => 15/390970 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 21183 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12175582 [patent_doc_number] => 09893732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Techniques for bypassing defects in rows of circuits' [patent_app_type] => utility [patent_app_number] => 15/389292 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12196260 [patent_doc_number] => 09900006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Semiconductor device, computer, and electronic device' [patent_app_type] => utility [patent_app_number] => 15/387132 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 80 [patent_no_of_words] => 29463 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14013247 [patent_doc_number] => 10225110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Transmission device, transmission method, and communication system [patent_app_type] => utility [patent_app_number] => 16/063439 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 16745 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16063439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11926304 [patent_doc_number] => 09793899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Mitigation of single event latchup' [patent_app_type] => utility [patent_app_number] => 15/382385 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13365685 [patent_doc_number] => 20180234383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SYSTEM AND METHOD FOR ADDRESS-MAPPED CONTROL OF FIELD PROGRAMMABLE GATE ARRAY (FPGA) VIA ETHERNET [patent_app_type] => utility [patent_app_number] => 15/379065 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11811923 [patent_doc_number] => 09716502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Protection of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 15/379155 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12336879 [patent_doc_number] => 09948298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Impedance calibration circuit and semiconductor apparatus including the same [patent_app_type] => utility [patent_app_number] => 15/377225 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4230 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12013369 [patent_doc_number] => 09806698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Circuit and method for a zero static current level shifter' [patent_app_type] => utility [patent_app_number] => 15/376751 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6113 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11718882 [patent_doc_number] => 20170187381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'ELECTRONIC CIRCUIT, LATCH CIRCUIT, AND EXTERNAL ACTION DETECTING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/376208 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3808 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376208 [rel_patent_id] =>[rel_patent_doc_number] =>)