Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6068392 [patent_doc_number] => 20110043241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Light emitting bio-mimicry device' [patent_app_type] => utility [patent_app_number] => 12/661208 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7289 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20110043241.pdf [firstpage_image] =>[orig_patent_app_number] => 12661208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/661208
Light emitting bio-mimicry device Mar 10, 2010 Issued
Array ( [id] => 6396052 [patent_doc_number] => 20100164546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'CIRCUIT SYSTEM INCLUDING FIRST CIRCUIT SUB-SYSTEM, SECOND CIRCUIT SUB-SYSTEM AND BIDIRECTIONAL BUS, CIRCUIT SUB-SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/719944 [patent_app_country] => US [patent_app_date] => 2010-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164546.pdf [firstpage_image] =>[orig_patent_app_number] => 12719944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719944
Circuit system including first circuit sub-system, second circuit sub-system and bidirectional bus, circuit sub-system and method Mar 8, 2010 Issued
Array ( [id] => 8376014 [patent_doc_number] => 08258815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Clock generator circuits for generating clock signals' [patent_app_type] => utility [patent_app_number] => 12/716912 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716912
Clock generator circuits for generating clock signals Mar 2, 2010 Issued
Array ( [id] => 6618993 [patent_doc_number] => 20100225356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'LATCH CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/715815 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20100225356.pdf [firstpage_image] =>[orig_patent_app_number] => 12715815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715815
Latch circuit Mar 1, 2010 Issued
Array ( [id] => 10145686 [patent_doc_number] => 09178505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Cross point switch' [patent_app_type] => utility [patent_app_number] => 12/715105 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12715105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715105
Cross point switch Feb 28, 2010 Issued
Array ( [id] => 7667179 [patent_doc_number] => 20110316448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'SYSTEM AND APPARATUS FOR CONTROLLING LIGHT INTENSITY OUTPUT OF LIGHT EMITTING DIODE ARRAYS' [patent_app_type] => utility [patent_app_number] => 13/255118 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5503 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13255118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/255118
SYSTEM AND APPARATUS FOR CONTROLLING LIGHT INTENSITY OUTPUT OF LIGHT EMITTING DIODE ARRAYS Feb 22, 2010 Abandoned
Array ( [id] => 6184802 [patent_doc_number] => 20110169527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING OUTPUT DRIVER' [patent_app_type] => utility [patent_app_number] => 12/708734 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5010 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20110169527.pdf [firstpage_image] =>[orig_patent_app_number] => 12708734 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708734
Semiconductor device having output driver Feb 18, 2010 Issued
Array ( [id] => 4554726 [patent_doc_number] => 07961009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Domino logic block having data holding function and domino logic including the domino logic block' [patent_app_type] => utility [patent_app_number] => 12/708882 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6180 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961009.pdf [firstpage_image] =>[orig_patent_app_number] => 12708882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708882
Domino logic block having data holding function and domino logic including the domino logic block Feb 18, 2010 Issued
Array ( [id] => 4587974 [patent_doc_number] => 07852107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Single event upset mitigation' [patent_app_type] => utility [patent_app_number] => 12/707935 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852107.pdf [firstpage_image] =>[orig_patent_app_number] => 12707935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/707935
Single event upset mitigation Feb 17, 2010 Issued
Array ( [id] => 6403828 [patent_doc_number] => 20100148816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Semiconductor integrated circuit device and testing method of the same' [patent_app_type] => utility [patent_app_number] => 12/656696 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9676 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148816.pdf [firstpage_image] =>[orig_patent_app_number] => 12656696 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656696
Semiconductor integrated circuit device and testing method of the same Feb 11, 2010 Issued
Array ( [id] => 6162209 [patent_doc_number] => 20110193588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/703793 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5103 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193588.pdf [firstpage_image] =>[orig_patent_app_number] => 12703793 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703793
Multi-mode circuit and a method for preventing degradation in the multi-mode circuit Feb 10, 2010 Issued
Array ( [id] => 4463201 [patent_doc_number] => 07880496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-01 [patent_title] => 'Conservative logic gate for design of quantum dot cellular automata circuits' [patent_app_type] => utility [patent_app_number] => 12/702587 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880496.pdf [firstpage_image] =>[orig_patent_app_number] => 12702587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702587
Conservative logic gate for design of quantum dot cellular automata circuits Feb 8, 2010 Issued
Array ( [id] => 4500768 [patent_doc_number] => 07948267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Efficient rounding circuits and methods in configurable integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 12/702445 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5029 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948267.pdf [firstpage_image] =>[orig_patent_app_number] => 12702445 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702445
Efficient rounding circuits and methods in configurable integrated circuit devices Feb 8, 2010 Issued
Array ( [id] => 4605183 [patent_doc_number] => 07986165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-26 [patent_title] => 'Voltage level shifter with dynamic circuit structure having discharge delay tracking' [patent_app_type] => utility [patent_app_number] => 12/701754 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8235 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986165.pdf [firstpage_image] =>[orig_patent_app_number] => 12701754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701754
Voltage level shifter with dynamic circuit structure having discharge delay tracking Feb 7, 2010 Issued
Array ( [id] => 6499317 [patent_doc_number] => 20100201398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'APPARATUS FOR PROVIDING A COMBINED DIGITAL SIGNAL' [patent_app_type] => utility [patent_app_number] => 12/701196 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 20076 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20100201398.pdf [firstpage_image] =>[orig_patent_app_number] => 12701196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701196
Apparatus for providing a combined digital signal Feb 4, 2010 Issued
Array ( [id] => 6287261 [patent_doc_number] => 20100237900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Semiconductor integrated circuit including a power controllable region' [patent_app_type] => utility [patent_app_number] => 12/656596 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10013 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237900.pdf [firstpage_image] =>[orig_patent_app_number] => 12656596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656596
Semiconductor integrated circuit including a power controllable region Feb 3, 2010 Issued
Array ( [id] => 4518819 [patent_doc_number] => 07932743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-26 [patent_title] => 'Sequentially configurable programmable integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/699703 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8860 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932743.pdf [firstpage_image] =>[orig_patent_app_number] => 12699703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699703
Sequentially configurable programmable integrated circuit Feb 2, 2010 Issued
Array ( [id] => 4576982 [patent_doc_number] => 07859309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Clock tree distributing method' [patent_app_type] => utility [patent_app_number] => 12/698366 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3773 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859309.pdf [firstpage_image] =>[orig_patent_app_number] => 12698366 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698366
Clock tree distributing method Feb 1, 2010 Issued
Array ( [id] => 6312078 [patent_doc_number] => 20100194204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/698567 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20100194204.pdf [firstpage_image] =>[orig_patent_app_number] => 12698567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698567
Semiconductor device Feb 1, 2010 Issued
Array ( [id] => 4528313 [patent_doc_number] => 07952381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/697777 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9988 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952381.pdf [firstpage_image] =>[orig_patent_app_number] => 12697777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697777
Semiconductor device Jan 31, 2010 Issued
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