
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6467553
[patent_doc_number] => 20100007374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 12/172282
[patent_app_country] => US
[patent_app_date] => 2008-07-14
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20100007374.pdf
[firstpage_image] =>[orig_patent_app_number] => 12172282
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172282 | ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE | Jul 13, 2008 | Abandoned |
Array
(
[id] => 7742317
[patent_doc_number] => 08106680
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-01-31
[patent_title] => 'Programmable logic device with a self-power down mechanism'
[patent_app_type] => utility
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[patent_app_date] => 2008-07-11
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[pdf_file] => patents/08/106/08106680.pdf
[firstpage_image] =>[orig_patent_app_number] => 12172054
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172054 | Programmable logic device with a self-power down mechanism | Jul 10, 2008 | Issued |
Array
(
[id] => 113153
[patent_doc_number] => 07719307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-18
[patent_title] => 'Data output driving circuit of semiconductor apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/172128
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 12172128
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172128 | Data output driving circuit of semiconductor apparatus | Jul 10, 2008 | Issued |
Array
(
[id] => 4884470
[patent_doc_number] => 20080258802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-23
[patent_title] => 'ADJUSTABLE TRANSISTOR BODY BIAS CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 12/163695
[patent_app_country] => US
[patent_app_date] => 2008-06-27
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12163695
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/163695 | Adjustable transistor body bias circuitry | Jun 26, 2008 | Issued |
Array
(
[id] => 4757205
[patent_doc_number] => 20080309430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'LOW-LOSS TUNABLE RADIO FREQUENCY FILTER'
[patent_app_type] => utility
[patent_app_number] => 12/163814
[patent_app_country] => US
[patent_app_date] => 2008-06-27
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[pdf_file] => publications/A1/0309/20080309430.pdf
[firstpage_image] =>[orig_patent_app_number] => 12163814
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/163814 | Low-loss tunable radio frequency filter | Jun 26, 2008 | Issued |
Array
(
[id] => 4661428
[patent_doc_number] => 20080252335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'ROBUST AND ECONOMIC SOLUTION FOR FPGA BITFILE UPGRADE'
[patent_app_type] => utility
[patent_app_number] => 12/144493
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[pdf_file] => publications/A1/0252/20080252335.pdf
[firstpage_image] =>[orig_patent_app_number] => 12144493
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/144493 | Robust and economic solution for FPGA bit file upgrade | Jun 22, 2008 | Issued |
Array
(
[id] => 4757144
[patent_doc_number] => 20080309369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM'
[patent_app_type] => utility
[patent_app_number] => 12/133969
[patent_app_country] => US
[patent_app_date] => 2008-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 15753
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[pdf_file] => publications/A1/0309/20080309369.pdf
[firstpage_image] =>[orig_patent_app_number] => 12133969
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133969 | Semiconductor integrated circuits with power reduction mechanism | Jun 4, 2008 | Issued |
Array
(
[id] => 4680284
[patent_doc_number] => 20080246510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS'
[patent_app_type] => utility
[patent_app_number] => 12/131258
[patent_app_country] => US
[patent_app_date] => 2008-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5709
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[pdf_file] => publications/A1/0246/20080246510.pdf
[firstpage_image] =>[orig_patent_app_number] => 12131258
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/131258 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Jun 1, 2008 | Issued |
Array
(
[id] => 8029667
[patent_doc_number] => 08143918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-27
[patent_title] => 'Apparatus for driving a display device, display device including the same, and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/131464
[patent_app_country] => US
[patent_app_date] => 2008-06-02
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[pdf_file] => patents/08/143/08143918.pdf
[firstpage_image] =>[orig_patent_app_number] => 12131464
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/131464 | Apparatus for driving a display device, display device including the same, and method thereof | Jun 1, 2008 | Issued |
Array
(
[id] => 4737667
[patent_doc_number] => 20080231319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY'
[patent_app_type] => utility
[patent_app_number] => 12/131722
[patent_app_country] => US
[patent_app_date] => 2008-06-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/131722 | DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY | Jun 1, 2008 | Abandoned |
Array
(
[id] => 178481
[patent_doc_number] => 07656191
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[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Distributed memory in field-programmable gate array integrated circuit devices'
[patent_app_type] => utility
[patent_app_number] => 12/156403
[patent_app_country] => US
[patent_app_date] => 2008-05-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/156403 | Distributed memory in field-programmable gate array integrated circuit devices | May 29, 2008 | Issued |
Array
(
[id] => 4696031
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[patent_kind] => A1
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[patent_title] => 'Advanced Repeater Utilizing Signal Distribution Delay'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/124136 | Advanced repeater utilizing signal distribution delay | May 19, 2008 | Issued |
Array
(
[id] => 123136
[patent_doc_number] => 07710147
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[patent_kind] => B1
[patent_issue_date] => 2010-05-04
[patent_title] => 'Techniques for configuring programmable logic using on-chip nonvolatile memory'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/122723 | Techniques for configuring programmable logic using on-chip nonvolatile memory | May 18, 2008 | Issued |
Array
(
[id] => 143084
[patent_doc_number] => 07688116
[patent_country] => US
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[patent_issue_date] => 2010-03-30
[patent_title] => 'Read data path'
[patent_app_type] => utility
[patent_app_number] => 12/151868
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/151868 | Read data path | May 8, 2008 | Issued |
Array
(
[id] => 8458820
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[patent_kind] => B2
[patent_issue_date] => 2012-10-23
[patent_title] => 'Ultra-low-power circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/598365 | Ultra-low-power circuit | Apr 28, 2008 | Issued |
Array
(
[id] => 6286995
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[patent_issue_date] => 2010-09-23
[patent_title] => 'DISCHARGE TUBE POWER SUPPLY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/294548 | Discharge tube power supply apparatus and semiconductor integrated circuit | Apr 22, 2008 | Issued |
Array
(
[id] => 4674754
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[patent_title] => 'Crossbar waveform driver circuit'
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/060791 | Integrated circuits with jitter-reducing balancing logic | Mar 31, 2008 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/059906 | Current driver suitable for use in a shared bus environment | Mar 30, 2008 | Issued |