
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4843922
[patent_doc_number] => 20080180330
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Multi-band antenna'
[patent_app_type] => utility
[patent_app_number] => 12/003447
[patent_app_country] => US
[patent_app_date] => 2007-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3115
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20080180330.pdf
[firstpage_image] =>[orig_patent_app_number] => 12003447
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/003447 | Multi-band antenna | Dec 25, 2007 | Issued |
Array
(
[id] => 4750021
[patent_doc_number] => 20080158092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Antenna and semiconductor device having the same'
[patent_app_type] => utility
[patent_app_number] => 12/000825
[patent_app_country] => US
[patent_app_date] => 2007-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13845
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20080158092.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000825
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000825 | Antenna and semiconductor device having the same | Dec 17, 2007 | Abandoned |
Array
(
[id] => 240122
[patent_doc_number] => 07592842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'Configurable delay chain with stacked inverter delay elements'
[patent_app_type] => utility
[patent_app_number] => 12/002988
[patent_app_country] => US
[patent_app_date] => 2007-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5362
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/592/07592842.pdf
[firstpage_image] =>[orig_patent_app_number] => 12002988
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/002988 | Configurable delay chain with stacked inverter delay elements | Dec 17, 2007 | Issued |
Array
(
[id] => 6338560
[patent_doc_number] => 20100019683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'METHOD AND DEVICE FOR DRIVING A GAS DISCHARGE LAMP'
[patent_app_type] => utility
[patent_app_number] => 12/519429
[patent_app_country] => US
[patent_app_date] => 2007-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5566
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20100019683.pdf
[firstpage_image] =>[orig_patent_app_number] => 12519429
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/519429 | METHOD AND DEVICE FOR DRIVING A GAS DISCHARGE LAMP | Dec 16, 2007 | Abandoned |
Array
(
[id] => 6549951
[patent_doc_number] => 20100045191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'DEVICE FOR CONTROLLING LIGHT SOURCES'
[patent_app_type] => utility
[patent_app_number] => 12/519440
[patent_app_country] => US
[patent_app_date] => 2007-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4337
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20100045191.pdf
[firstpage_image] =>[orig_patent_app_number] => 12519440
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/519440 | DEVICE FOR CONTROLLING LIGHT SOURCES | Dec 16, 2007 | Abandoned |
Array
(
[id] => 6549914
[patent_doc_number] => 20100045188
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-25
[patent_title] => 'ADJUSTING A DRIVING SIGNAL FOR SOLID-STATE LIGHTING DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/519391
[patent_app_country] => US
[patent_app_date] => 2007-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2673
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20100045188.pdf
[firstpage_image] =>[orig_patent_app_number] => 12519391
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/519391 | ADJUSTING A DRIVING SIGNAL FOR SOLID-STATE LIGHTING DEVICES | Dec 13, 2007 | Abandoned |
Array
(
[id] => 296557
[patent_doc_number] => 07541831
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-02
[patent_title] => 'Semiconductor memory device for adjusting impedance of data output driver'
[patent_app_type] => utility
[patent_app_number] => 11/987937
[patent_app_country] => US
[patent_app_date] => 2007-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 7796
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/541/07541831.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987937
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987937 | Semiconductor memory device for adjusting impedance of data output driver | Dec 5, 2007 | Issued |
Array
(
[id] => 240119
[patent_doc_number] => 07592839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability'
[patent_app_type] => utility
[patent_app_number] => 11/999293
[patent_app_country] => US
[patent_app_date] => 2007-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3244
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/592/07592839.pdf
[firstpage_image] =>[orig_patent_app_number] => 11999293
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/999293 | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability | Dec 3, 2007 | Issued |
Array
(
[id] => 4864326
[patent_doc_number] => 20080143385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion'
[patent_app_type] => utility
[patent_app_number] => 11/986980
[patent_app_country] => US
[patent_app_date] => 2007-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5577
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20080143385.pdf
[firstpage_image] =>[orig_patent_app_number] => 11986980
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/986980 | Method and circuitry to translate a differential logic signal to a CMOS logic signal | Nov 26, 2007 | Issued |
Array
(
[id] => 7595040
[patent_doc_number] => 07626421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Interface circuit and electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/934091
[patent_app_country] => US
[patent_app_date] => 2007-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3421
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/626/07626421.pdf
[firstpage_image] =>[orig_patent_app_number] => 11934091
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934091 | Interface circuit and electronic device | Nov 1, 2007 | Issued |
Array
(
[id] => 4963477
[patent_doc_number] => 20080106297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-08
[patent_title] => 'SLEW RATE CONTROLLED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 11/933451
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 4161
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20080106297.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933451
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933451 | SLEW RATE CONTROLLED CIRCUITS | Oct 31, 2007 | Abandoned |
Array
(
[id] => 5262762
[patent_doc_number] => 20090115447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/933646
[patent_app_country] => US
[patent_app_date] => 2007-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4383
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20090115447.pdf
[firstpage_image] =>[orig_patent_app_number] => 11933646
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/933646 | Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit | Oct 31, 2007 | Abandoned |
Array
(
[id] => 4700158
[patent_doc_number] => 20080222342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'Crossbar comparator'
[patent_app_type] => utility
[patent_app_number] => 11/976925
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1851
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20080222342.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976925
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976925 | Crossbar comparator | Oct 29, 2007 | Issued |
Array
(
[id] => 4774026
[patent_doc_number] => 20080059688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'Crossbar control circuit'
[patent_app_type] => utility
[patent_app_number] => 11/976927
[patent_app_country] => US
[patent_app_date] => 2007-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1895
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20080059688.pdf
[firstpage_image] =>[orig_patent_app_number] => 11976927
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976927 | Crossbar control circuit | Oct 29, 2007 | Issued |
Array
(
[id] => 233343
[patent_doc_number] => 07598773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-06
[patent_title] => 'Radiation hardened logic circuits'
[patent_app_type] => utility
[patent_app_number] => 11/926622
[patent_app_country] => US
[patent_app_date] => 2007-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4659
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/598/07598773.pdf
[firstpage_image] =>[orig_patent_app_number] => 11926622
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/926622 | Radiation hardened logic circuits | Oct 28, 2007 | Issued |
Array
(
[id] => 243819
[patent_doc_number] => 07589556
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-09-15
[patent_title] => 'Dynamic control of memory interface timing'
[patent_app_type] => utility
[patent_app_number] => 11/925717
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4424
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/589/07589556.pdf
[firstpage_image] =>[orig_patent_app_number] => 11925717
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/925717 | Dynamic control of memory interface timing | Oct 25, 2007 | Issued |
Array
(
[id] => 253226
[patent_doc_number] => 07579862
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-25
[patent_title] => 'MOS linear region impedance curvature correction'
[patent_app_type] => utility
[patent_app_number] => 11/974925
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 32
[patent_no_of_words] => 15926
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/579/07579862.pdf
[firstpage_image] =>[orig_patent_app_number] => 11974925
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/974925 | MOS linear region impedance curvature correction | Oct 15, 2007 | Issued |
Array
(
[id] => 84889
[patent_doc_number] => 07741878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Semiconductor integrated circuit with leakage current suppressed'
[patent_app_type] => utility
[patent_app_number] => 11/907212
[patent_app_country] => US
[patent_app_date] => 2007-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 4811
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/741/07741878.pdf
[firstpage_image] =>[orig_patent_app_number] => 11907212
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907212 | Semiconductor integrated circuit with leakage current suppressed | Oct 9, 2007 | Issued |
Array
(
[id] => 4919768
[patent_doc_number] => 20080068081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'High-voltage operational amplifier input stage and method'
[patent_app_type] => utility
[patent_app_number] => 11/901847
[patent_app_country] => US
[patent_app_date] => 2007-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7309
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20080068081.pdf
[firstpage_image] =>[orig_patent_app_number] => 11901847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/901847 | High-voltage operational amplifier input stage and method | Sep 18, 2007 | Issued |
Array
(
[id] => 4953030
[patent_doc_number] => 20080186054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH'
[patent_app_type] => utility
[patent_app_number] => 11/848470
[patent_app_country] => US
[patent_app_date] => 2007-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12624
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20080186054.pdf
[firstpage_image] =>[orig_patent_app_number] => 11848470
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/848470 | Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path | Aug 30, 2007 | Issued |