
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 920252
[patent_doc_number] => 07321238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-01-22
[patent_title] => 'Over-voltage tolerant multifunction input stage'
[patent_app_type] => utility
[patent_app_number] => 11/317066
[patent_app_country] => US
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[pdf_file] => patents/07/321/07321238.pdf
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Array
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[patent_app_type] => utility
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Array
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[patent_title] => 'Dedicated input/output first in/first out module for a field programmable gate array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/295889 | Dedicated input/output first in/first out module for a field programmable gate array | Dec 5, 2005 | Issued |
Array
(
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[patent_doc_number] => 07746097
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[patent_issue_date] => 2010-06-29
[patent_title] => 'Transceiver having an adjustable terminating network for a control device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/884409 | Transceiver having an adjustable terminating network for a control device | Dec 1, 2005 | Issued |
Array
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[patent_title] => 'Semiconductor device provided with antenna ratio countermeasure circuit'
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Array
(
[id] => 821043
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[patent_title] => 'Calibration methods and circuits for optimized on-die termination'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/286229 | Calibration methods and circuits for optimized on-die termination | Nov 22, 2005 | Issued |
Array
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[patent_title] => 'Bootstrap circuit and driving method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274165 | Bootstrap circuit and driving method thereof | Nov 15, 2005 | Issued |
Array
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[id] => 380430
[patent_doc_number] => 07310006
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[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
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[pdf_file] => patents/07/310/07310006.pdf
[firstpage_image] =>[orig_patent_app_number] => 11274184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274184 | Semiconductor integrated circuit | Nov 15, 2005 | Issued |
Array
(
[id] => 429153
[patent_doc_number] => 07268591
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[patent_issue_date] => 2007-09-11
[patent_title] => 'Decode structure with parallel rotation'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274876 | Decode structure with parallel rotation | Nov 14, 2005 | Issued |
Array
(
[id] => 387135
[patent_doc_number] => 07304505
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[patent_title] => 'Output buffer stage'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11272847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/272847 | Output buffer stage | Nov 13, 2005 | Issued |
Array
(
[id] => 853749
[patent_doc_number] => 07378875
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[patent_title] => 'Compensation circuits for unequal input/output common mode voltages'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273026 | Compensation circuits for unequal input/output common mode voltages | Nov 13, 2005 | Issued |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/252126 | Field programmable gate array | Oct 16, 2005 | Issued |
Array
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[patent_title] => 'P-domino register'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/251384 | P-domino register | Oct 13, 2005 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/251399 | P-domino output latch | Oct 13, 2005 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/246280 | Lookup table circuit | Oct 10, 2005 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/239735 | Programmable logic device with routing channels | Sep 28, 2005 | Issued |