Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 920252 [patent_doc_number] => 07321238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-22 [patent_title] => 'Over-voltage tolerant multifunction input stage' [patent_app_type] => utility [patent_app_number] => 11/317066 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7047 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321238.pdf [firstpage_image] =>[orig_patent_app_number] => 11317066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317066
Over-voltage tolerant multifunction input stage Dec 21, 2005 Issued
Array ( [id] => 14867 [patent_doc_number] => 07808272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/296698 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10689 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808272.pdf [firstpage_image] =>[orig_patent_app_number] => 11296698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296698
Integrated circuit Dec 7, 2005 Issued
Array ( [id] => 5741618 [patent_doc_number] => 20060087341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Dedicated input/output first in/first out module for a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 11/295889 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4367 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087341.pdf [firstpage_image] =>[orig_patent_app_number] => 11295889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295889
Dedicated input/output first in/first out module for a field programmable gate array Dec 5, 2005 Issued
Array ( [id] => 83168 [patent_doc_number] => 07746097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Transceiver having an adjustable terminating network for a control device' [patent_app_type] => utility [patent_app_number] => 11/884409 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2125 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746097.pdf [firstpage_image] =>[orig_patent_app_number] => 11884409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/884409
Transceiver having an adjustable terminating network for a control device Dec 1, 2005 Issued
Array ( [id] => 5838911 [patent_doc_number] => 20060119395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Semiconductor device provided with antenna ratio countermeasure circuit' [patent_app_type] => utility [patent_app_number] => 11/290805 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 14218 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119395.pdf [firstpage_image] =>[orig_patent_app_number] => 11290805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/290805
Semiconductor device provided with antenna ratio countermeasure circuit Nov 30, 2005 Issued
Array ( [id] => 821043 [patent_doc_number] => 07408378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Calibration methods and circuits for optimized on-die termination' [patent_app_type] => utility [patent_app_number] => 11/286229 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3597 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408378.pdf [firstpage_image] =>[orig_patent_app_number] => 11286229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/286229
Calibration methods and circuits for optimized on-die termination Nov 22, 2005 Issued
Array ( [id] => 323173 [patent_doc_number] => 07518407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Bootstrap circuit and driving method thereof' [patent_app_type] => utility [patent_app_number] => 11/274165 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 10104 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518407.pdf [firstpage_image] =>[orig_patent_app_number] => 11274165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274165
Bootstrap circuit and driving method thereof Nov 15, 2005 Issued
Array ( [id] => 380430 [patent_doc_number] => 07310006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/274184 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9241 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310006.pdf [firstpage_image] =>[orig_patent_app_number] => 11274184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274184
Semiconductor integrated circuit Nov 15, 2005 Issued
Array ( [id] => 429153 [patent_doc_number] => 07268591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Decode structure with parallel rotation' [patent_app_type] => utility [patent_app_number] => 11/274876 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3138 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268591.pdf [firstpage_image] =>[orig_patent_app_number] => 11274876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/274876
Decode structure with parallel rotation Nov 14, 2005 Issued
Array ( [id] => 387135 [patent_doc_number] => 07304505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Output buffer stage' [patent_app_type] => utility [patent_app_number] => 11/272847 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304505.pdf [firstpage_image] =>[orig_patent_app_number] => 11272847 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272847
Output buffer stage Nov 13, 2005 Issued
Array ( [id] => 853749 [patent_doc_number] => 07378875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Compensation circuits for unequal input/output common mode voltages' [patent_app_type] => utility [patent_app_number] => 11/273026 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1339 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378875.pdf [firstpage_image] =>[orig_patent_app_number] => 11273026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/273026
Compensation circuits for unequal input/output common mode voltages Nov 13, 2005 Issued
Array ( [id] => 492226 [patent_doc_number] => 07215153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'Fully differential input buffer with wide signal swing range' [patent_app_type] => utility [patent_app_number] => 11/266207 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215153.pdf [firstpage_image] =>[orig_patent_app_number] => 11266207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266207
Fully differential input buffer with wide signal swing range Nov 3, 2005 Issued
Array ( [id] => 5796851 [patent_doc_number] => 20060033528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Field programmable gate array' [patent_app_type] => utility [patent_app_number] => 11/252126 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033528.pdf [firstpage_image] =>[orig_patent_app_number] => 11252126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252126
Field programmable gate array Oct 16, 2005 Issued
Array ( [id] => 527702 [patent_doc_number] => 07187210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'P-domino register' [patent_app_type] => utility [patent_app_number] => 11/251384 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10868 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187210.pdf [firstpage_image] =>[orig_patent_app_number] => 11251384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251384
P-domino register Oct 13, 2005 Issued
Array ( [id] => 5796857 [patent_doc_number] => 20060033534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'N-domino output latch' [patent_app_type] => utility [patent_app_number] => 11/251517 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11112 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033534.pdf [firstpage_image] =>[orig_patent_app_number] => 11251517 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251517
N-domino output latch Oct 13, 2005 Issued
Array ( [id] => 527710 [patent_doc_number] => 07187211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'P-domino output latch' [patent_app_type] => utility [patent_app_number] => 11/251399 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187211.pdf [firstpage_image] =>[orig_patent_app_number] => 11251399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251399
P-domino output latch Oct 13, 2005 Issued
Array ( [id] => 926031 [patent_doc_number] => 07317329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Lookup table circuit' [patent_app_type] => utility [patent_app_number] => 11/246280 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2055 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317329.pdf [firstpage_image] =>[orig_patent_app_number] => 11246280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246280
Lookup table circuit Oct 10, 2005 Issued
Array ( [id] => 4795785 [patent_doc_number] => 20080007371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'High Frequency Filter' [patent_app_type] => utility [patent_app_number] => 11/667864 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3824 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20080007371.pdf [firstpage_image] =>[orig_patent_app_number] => 11667864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/667864
High frequency filter Oct 5, 2005 Issued
Array ( [id] => 334817 [patent_doc_number] => 07508230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Digital programmable phase generator' [patent_app_type] => utility [patent_app_number] => 11/243020 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 1538 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508230.pdf [firstpage_image] =>[orig_patent_app_number] => 11243020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243020
Digital programmable phase generator Oct 3, 2005 Issued
Array ( [id] => 620604 [patent_doc_number] => 07142011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Programmable logic device with routing channels' [patent_app_type] => utility [patent_app_number] => 11/239735 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6082 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142011.pdf [firstpage_image] =>[orig_patent_app_number] => 11239735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239735
Programmable logic device with routing channels Sep 28, 2005 Issued
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