
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5736511
[patent_doc_number] => 20060006901
[patent_country] => US
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[patent_issue_date] => 2006-01-12
[patent_title] => 'DAC based driver with selectable pre-emphasis signal levels'
[patent_app_type] => utility
[patent_app_number] => 11/218962
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Array
(
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[patent_issue_date] => 2007-02-22
[patent_title] => 'Word line driver with reduced leakage current'
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Array
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[patent_title] => 'Programmable logic device with routing channels'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/208906 | Programmable logic device with routing channels | Aug 21, 2005 | Issued |
Array
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[patent_title] => 'High speed, low power CMOS logic gate'
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Array
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Array
(
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[patent_title] => 'Robust and economic solution for FPGA bitfile upgrade'
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Array
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Array
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[id] => 377535
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[patent_title] => 'Enhanced timing margin memory interface'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/206638 | Enhanced timing margin memory interface | Aug 16, 2005 | Issued |
Array
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[id] => 485008
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[patent_title] => 'Dynamic node keeper system and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/199950 | Dynamic node keeper system and method | Aug 7, 2005 | Issued |
Array
(
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[patent_title] => 'Advanced repeater utilizing signal distribution delay'
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Array
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[id] => 824123
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[patent_title] => 'Advanced repeater with duty cycle adjustment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172013 | Advanced repeater with duty cycle adjustment | Jun 29, 2005 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/145135 | Method and apparatus for a configurable latch | Jun 2, 2005 | Issued |
Array
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Array
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