Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5736511 [patent_doc_number] => 20060006901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'DAC based driver with selectable pre-emphasis signal levels' [patent_app_type] => utility [patent_app_number] => 11/218962 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8230 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006901.pdf [firstpage_image] =>[orig_patent_app_number] => 11218962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218962
DAC based driver with selectable pre-emphasis signal levels Aug 31, 2005 Issued
Array ( [id] => 4997947 [patent_doc_number] => 20070040581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Word line driver with reduced leakage current' [patent_app_type] => utility [patent_app_number] => 11/208575 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040581.pdf [firstpage_image] =>[orig_patent_app_number] => 11208575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208575
Word line driver with reduced leakage current Aug 21, 2005 Issued
Array ( [id] => 474461 [patent_doc_number] => 07230451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Programmable logic device with routing channels' [patent_app_type] => utility [patent_app_number] => 11/208906 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8267 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230451.pdf [firstpage_image] =>[orig_patent_app_number] => 11208906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208906
Programmable logic device with routing channels Aug 21, 2005 Issued
Array ( [id] => 4997951 [patent_doc_number] => 20070040585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'High speed, low power CMOS logic gate' [patent_app_type] => utility [patent_app_number] => 11/207806 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3819 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040585.pdf [firstpage_image] =>[orig_patent_app_number] => 11207806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207806
High speed, low power CMOS logic gate Aug 21, 2005 Issued
Array ( [id] => 717627 [patent_doc_number] => 07053661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Impedance-matched output driver circuits having enhanced predriver control' [patent_app_type] => utility [patent_app_number] => 11/207370 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5117 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053661.pdf [firstpage_image] =>[orig_patent_app_number] => 11207370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207370
Impedance-matched output driver circuits having enhanced predriver control Aug 18, 2005 Issued
Array ( [id] => 5832654 [patent_doc_number] => 20060244484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Robust and economic solution for FPGA bitfile upgrade' [patent_app_type] => utility [patent_app_number] => 11/207355 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4084 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20060244484.pdf [firstpage_image] =>[orig_patent_app_number] => 11207355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207355
Robust and economic solution for FPGA bitfile upgrade Aug 17, 2005 Issued
Array ( [id] => 4997946 [patent_doc_number] => 20070040580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Reference buffer with improved drift' [patent_app_type] => utility [patent_app_number] => 11/206406 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040580.pdf [firstpage_image] =>[orig_patent_app_number] => 11206406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206406
Reference buffer with improved drift Aug 17, 2005 Issued
Array ( [id] => 377535 [patent_doc_number] => 07312637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Enhanced timing margin memory interface' [patent_app_type] => utility [patent_app_number] => 11/206638 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1803 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312637.pdf [firstpage_image] =>[orig_patent_app_number] => 11206638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206638
Enhanced timing margin memory interface Aug 16, 2005 Issued
Array ( [id] => 485008 [patent_doc_number] => 07221189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'Dynamic node keeper system and method' [patent_app_type] => utility [patent_app_number] => 11/199950 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3992 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221189.pdf [firstpage_image] =>[orig_patent_app_number] => 11199950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199950
Dynamic node keeper system and method Aug 7, 2005 Issued
Array ( [id] => 857707 [patent_doc_number] => 07375556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Advanced repeater utilizing signal distribution delay' [patent_app_type] => utility [patent_app_number] => 11/171845 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2363 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/375/07375556.pdf [firstpage_image] =>[orig_patent_app_number] => 11171845 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171845
Advanced repeater utilizing signal distribution delay Jun 29, 2005 Issued
Array ( [id] => 824123 [patent_doc_number] => 07405597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-29 [patent_title] => 'Advanced repeater with duty cycle adjustment' [patent_app_type] => utility [patent_app_number] => 11/172013 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405597.pdf [firstpage_image] =>[orig_patent_app_number] => 11172013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172013
Advanced repeater with duty cycle adjustment Jun 29, 2005 Issued
Array ( [id] => 726294 [patent_doc_number] => 07046037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-16 [patent_title] => 'Differential input buffers with elevated power supplies' [patent_app_type] => utility [patent_app_number] => 11/153676 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046037.pdf [firstpage_image] =>[orig_patent_app_number] => 11153676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153676
Differential input buffers with elevated power supplies Jun 14, 2005 Issued
Array ( [id] => 5008644 [patent_doc_number] => 20070279121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Signal Output Circuit' [patent_app_type] => utility [patent_app_number] => 11/664097 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5280 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279121.pdf [firstpage_image] =>[orig_patent_app_number] => 11664097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/664097
Signal output circuit Jun 2, 2005 Issued
Array ( [id] => 447984 [patent_doc_number] => 07253661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-07 [patent_title] => 'Method and apparatus for a configurable latch' [patent_app_type] => utility [patent_app_number] => 11/145135 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253661.pdf [firstpage_image] =>[orig_patent_app_number] => 11145135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145135
Method and apparatus for a configurable latch Jun 2, 2005 Issued
Array ( [id] => 767542 [patent_doc_number] => 07009423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Programmable I/O interfaces for FPGAs and other PLDs' [patent_app_type] => utility [patent_app_number] => 11/134152 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009423.pdf [firstpage_image] =>[orig_patent_app_number] => 11134152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134152
Programmable I/O interfaces for FPGAs and other PLDs May 19, 2005 Issued
Array ( [id] => 4725569 [patent_doc_number] => 20080205110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Digital Magnetic Current Sensor and Logic' [patent_app_type] => utility [patent_app_number] => 11/596791 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205110.pdf [firstpage_image] =>[orig_patent_app_number] => 11596791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596791
Digital magnetic current sensor and logic May 10, 2005 Issued
Array ( [id] => 549080 [patent_doc_number] => 07167017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion in a power-up mode' [patent_app_type] => utility [patent_app_number] => 10/908307 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2980 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167017.pdf [firstpage_image] =>[orig_patent_app_number] => 10908307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908307
Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion in a power-up mode May 5, 2005 Issued
Array ( [id] => 7177808 [patent_doc_number] => 20050189964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Output buffer circuit and control method therefor' [patent_app_type] => utility [patent_app_number] => 11/121130 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10048 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189964.pdf [firstpage_image] =>[orig_patent_app_number] => 11121130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/121130
Output buffer circuit and control method therefor May 3, 2005 Issued
Array ( [id] => 692389 [patent_doc_number] => 07075334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks' [patent_app_type] => utility [patent_app_number] => 11/120509 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5662 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075334.pdf [firstpage_image] =>[orig_patent_app_number] => 11120509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/120509
Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks May 1, 2005 Issued
Array ( [id] => 5624085 [patent_doc_number] => 20060262590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'One-time programmable circuit exploiting BJT hFE degradation' [patent_app_type] => utility [patent_app_number] => 11/115538 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3102 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262590.pdf [firstpage_image] =>[orig_patent_app_number] => 11115538 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115538
One-time programmable circuit exploiting BJT hFE degradation Apr 26, 2005 Issued
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