
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7601283
[patent_doc_number] => 07385423
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-06-10
[patent_title] => 'Low-power low-voltage buffer with half-latch'
[patent_app_type] => utility
[patent_app_number] => 11/114827
[patent_app_country] => US
[patent_app_date] => 2005-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1670
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/385/07385423.pdf
[firstpage_image] =>[orig_patent_app_number] => 11114827
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/114827 | Low-power low-voltage buffer with half-latch | Apr 25, 2005 | Issued |
Array
(
[id] => 7048867
[patent_doc_number] => 20050184754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 11/109966
[patent_app_country] => US
[patent_app_date] => 2005-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3761
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20050184754.pdf
[firstpage_image] =>[orig_patent_app_number] => 11109966
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/109966 | Field programmable gate array | Apr 18, 2005 | Issued |
Array
(
[id] => 643156
[patent_doc_number] => 07123055
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-17
[patent_title] => 'Impedance-matched output driver circuits having coarse and fine tuning control'
[patent_app_type] => utility
[patent_app_number] => 11/105237
[patent_app_country] => US
[patent_app_date] => 2005-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6364
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/123/07123055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11105237
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/105237 | Impedance-matched output driver circuits having coarse and fine tuning control | Apr 12, 2005 | Issued |
Array
(
[id] => 833983
[patent_doc_number] => 07397274
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-07-08
[patent_title] => 'In-system programming of a non-compliant device using multiple interfaces of a PLD'
[patent_app_type] => utility
[patent_app_number] => 11/100718
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6828
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/397/07397274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100718
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100718 | In-system programming of a non-compliant device using multiple interfaces of a PLD | Apr 6, 2005 | Issued |
Array
(
[id] => 5854560
[patent_doc_number] => 20060226493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs'
[patent_app_type] => utility
[patent_app_number] => 11/100883
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1794
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20060226493.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100883
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100883 | High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs | Apr 6, 2005 | Issued |
Array
(
[id] => 5718912
[patent_doc_number] => 20060071685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Integrated Circuit Chip With High Area Utilization Rate'
[patent_app_type] => utility
[patent_app_number] => 10/907608
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2396
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20060071685.pdf
[firstpage_image] =>[orig_patent_app_number] => 10907608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907608 | Integrated circuit chip with high area utilization rate | Apr 6, 2005 | Issued |
Array
(
[id] => 440526
[patent_doc_number] => 07259592
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-21
[patent_title] => 'Output drivers having adjustable swing widths during test mode operation'
[patent_app_type] => utility
[patent_app_number] => 11/098818
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 9992
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/259/07259592.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098818
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098818 | Output drivers having adjustable swing widths during test mode operation | Apr 4, 2005 | Issued |
Array
(
[id] => 923371
[patent_doc_number] => 07319343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-15
[patent_title] => 'Low power scan design and delay fault testing technique using first level supply gating'
[patent_app_type] => utility
[patent_app_number] => 11/099386
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10286
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/319/07319343.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099386 | Low power scan design and delay fault testing technique using first level supply gating | Apr 4, 2005 | Issued |
Array
(
[id] => 444074
[patent_doc_number] => 07256619
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-08-14
[patent_title] => 'Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode'
[patent_app_type] => utility
[patent_app_number] => 11/099186
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4805
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/256/07256619.pdf
[firstpage_image] =>[orig_patent_app_number] => 11099186
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/099186 | Apparatus to shift to pre-charge mode a dynamic circuit driven by one-shot clock signal during power off mode | Apr 3, 2005 | Issued |
Array
(
[id] => 527555
[patent_doc_number] => 07187197
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-06
[patent_title] => 'Transmission line driver'
[patent_app_type] => utility
[patent_app_number] => 11/098108
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2279
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/187/07187197.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098108
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098108 | Transmission line driver | Apr 3, 2005 | Issued |
Array
(
[id] => 432801
[patent_doc_number] => 07265578
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-04
[patent_title] => 'In-system programming of non-JTAG device using SPI and JTAG interfaces of FPGA device'
[patent_app_type] => utility
[patent_app_number] => 11/098713
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7301
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/265/07265578.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098713
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098713 | In-system programming of non-JTAG device using SPI and JTAG interfaces of FPGA device | Apr 3, 2005 | Issued |
Array
(
[id] => 387124
[patent_doc_number] => 07304494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-04
[patent_title] => 'Methods and apparatus to DC couple LVDS driver to CML levels'
[patent_app_type] => utility
[patent_app_number] => 11/098832
[patent_app_country] => US
[patent_app_date] => 2005-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1820
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/304/07304494.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098832
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098832 | Methods and apparatus to DC couple LVDS driver to CML levels | Apr 3, 2005 | Issued |
Array
(
[id] => 5755871
[patent_doc_number] => 20060225020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Methods and apparatus for 3-D FPGA design'
[patent_app_type] => utility
[patent_app_number] => 11/097363
[patent_app_country] => US
[patent_app_date] => 2005-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4964
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20060225020.pdf
[firstpage_image] =>[orig_patent_app_number] => 11097363
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/097363 | Methods and apparatus for 3-D FPGA design | Mar 31, 2005 | Abandoned |
Array
(
[id] => 5751536
[patent_doc_number] => 20060220685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'High speed driver for serial communications'
[patent_app_type] => utility
[patent_app_number] => 11/095882
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7587
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20060220685.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095882
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095882 | High speed driver for serial communications | Mar 30, 2005 | Issued |
Array
(
[id] => 5751528
[patent_doc_number] => 20060220677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Signal measurement systems and methods'
[patent_app_type] => utility
[patent_app_number] => 11/095951
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3734
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20060220677.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095951
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095951 | Signal measurement systems and methods | Mar 30, 2005 | Issued |
Array
(
[id] => 5751529
[patent_doc_number] => 20060220678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Method and system for elastic signal pipelining'
[patent_app_type] => utility
[patent_app_number] => 11/096354
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3871
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0220/20060220678.pdf
[firstpage_image] =>[orig_patent_app_number] => 11096354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/096354 | Method and system for elastic signal pipelining | Mar 30, 2005 | Issued |
Array
(
[id] => 425631
[patent_doc_number] => 07271614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Buffer circuit with current limiting'
[patent_app_type] => utility
[patent_app_number] => 11/094974
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 6223
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/271/07271614.pdf
[firstpage_image] =>[orig_patent_app_number] => 11094974
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/094974 | Buffer circuit with current limiting | Mar 30, 2005 | Issued |
Array
(
[id] => 440513
[patent_doc_number] => 07259587
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-08-21
[patent_title] => 'Configurable IC\'s with configurable logic resources that have asymetric inputs and/or outputs'
[patent_app_type] => utility
[patent_app_number] => 11/081861
[patent_app_country] => US
[patent_app_date] => 2005-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 50
[patent_no_of_words] => 22152
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/259/07259587.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081861 | Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs | Mar 14, 2005 | Issued |
Array
(
[id] => 6995406
[patent_doc_number] => 20050135184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'DISTRIBUTED CLOCK GENERATOR FOR SEMICONDUCTOR DEVICES AND RELATED METHODS OF OPERATING SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 10/906765
[patent_app_country] => US
[patent_app_date] => 2005-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4567
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20050135184.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906765
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906765 | Distributed clock generator for semiconductor devices and related methods of operating semiconductor devices | Mar 3, 2005 | Issued |
Array
(
[id] => 803742
[patent_doc_number] => 07423449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Electronic circuit'
[patent_app_type] => utility
[patent_app_number] => 10/598573
[patent_app_country] => US
[patent_app_date] => 2005-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1910
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/423/07423449.pdf
[firstpage_image] =>[orig_patent_app_number] => 10598573
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/598573 | Electronic circuit | Feb 23, 2005 | Issued |