Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 931522 [patent_doc_number] => 06980028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Dedicated input/output first in/first out module for a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 11/056983 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4334 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/980/06980028.pdf [firstpage_image] =>[orig_patent_app_number] => 11056983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056983
Dedicated input/output first in/first out module for a field programmable gate array Feb 10, 2005 Issued
Array ( [id] => 7098042 [patent_doc_number] => 20050130501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and system for reducing aggregate impedance discontinuity between expansion connectors' [patent_app_type] => utility [patent_app_number] => 11/048326 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3577 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130501.pdf [firstpage_image] =>[orig_patent_app_number] => 11048326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048326
Method and system for reducing aggregate impedance discontinuity between expansion connectors Jan 31, 2005 Issued
Array ( [id] => 549667 [patent_doc_number] => 07164289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Real time feedback compensation of programmable logic memory' [patent_app_type] => utility [patent_app_number] => 10/905830 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5161 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164289.pdf [firstpage_image] =>[orig_patent_app_number] => 10905830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905830
Real time feedback compensation of programmable logic memory Jan 20, 2005 Issued
Array ( [id] => 606928 [patent_doc_number] => 07154297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Programmable logic with programmable volatility' [patent_app_type] => utility [patent_app_number] => 10/905832 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5698 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/154/07154297.pdf [firstpage_image] =>[orig_patent_app_number] => 10905832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905832
Programmable logic with programmable volatility Jan 20, 2005 Issued
Array ( [id] => 696652 [patent_doc_number] => 07071731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-04 [patent_title] => 'Programmable Logic with Pipelined Memory Operation' [patent_app_type] => utility [patent_app_number] => 10/905831 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071731.pdf [firstpage_image] =>[orig_patent_app_number] => 10905831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905831
Programmable Logic with Pipelined Memory Operation Jan 20, 2005 Issued
Array ( [id] => 549165 [patent_doc_number] => 07167024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Methods and circuitry for implementing first-in first-out structure' [patent_app_type] => utility [patent_app_number] => 11/027864 [patent_app_country] => US [patent_app_date] => 2004-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167024.pdf [firstpage_image] =>[orig_patent_app_number] => 11027864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027864
Methods and circuitry for implementing first-in first-out structure Dec 30, 2004 Issued
Array ( [id] => 7141760 [patent_doc_number] => 20050117428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Methods and circuitry for implementing first-in first-out structure' [patent_app_type] => utility [patent_app_number] => 11/027848 [patent_app_country] => US [patent_app_date] => 2004-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5785 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20050117428.pdf [firstpage_image] =>[orig_patent_app_number] => 11027848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027848
Methods and circuitry for implementing first-in first-out structure Dec 30, 2004 Issued
Array ( [id] => 7172534 [patent_doc_number] => 20050122815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Methods and circuitry for implementing first-in first-out structure' [patent_app_type] => utility [patent_app_number] => 11/027193 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5787 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122815.pdf [firstpage_image] =>[orig_patent_app_number] => 11027193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027193
Methods and circuitry for implementing first-in first-out structure Dec 29, 2004 Issued
Array ( [id] => 7185090 [patent_doc_number] => 20050162187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Programmable I/O element circuit for high speed logic devices' [patent_app_type] => utility [patent_app_number] => 11/025774 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6918 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162187.pdf [firstpage_image] =>[orig_patent_app_number] => 11025774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025774
Programmable I/O element circuit for high speed logic devices Dec 28, 2004 Issued
Array ( [id] => 7095494 [patent_doc_number] => 20050127952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Non-inverting domino register' [patent_app_type] => utility [patent_app_number] => 11/023145 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7585 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127952.pdf [firstpage_image] =>[orig_patent_app_number] => 11023145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/023145
Non-inverting domino register Dec 26, 2004 Issued
Array ( [id] => 908650 [patent_doc_number] => 07332931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'Leakage efficient anti-glitch filter with variable delay stages' [patent_app_type] => utility [patent_app_number] => 11/021197 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5053 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332931.pdf [firstpage_image] =>[orig_patent_app_number] => 11021197 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021197
Leakage efficient anti-glitch filter with variable delay stages Dec 22, 2004 Issued
Array ( [id] => 380432 [patent_doc_number] => 07310008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Configurable delay chain with stacked inverter delay elements' [patent_app_type] => utility [patent_app_number] => 11/020746 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5353 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310008.pdf [firstpage_image] =>[orig_patent_app_number] => 11020746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020746
Configurable delay chain with stacked inverter delay elements Dec 22, 2004 Issued
Array ( [id] => 904720 [patent_doc_number] => 07336099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-26 [patent_title] => 'Multiplexer including addition element' [patent_app_type] => utility [patent_app_number] => 11/021685 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336099.pdf [firstpage_image] =>[orig_patent_app_number] => 11021685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021685
Multiplexer including addition element Dec 22, 2004 Issued
Array ( [id] => 911783 [patent_doc_number] => 07330054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Leakage efficient anti-glitch filter' [patent_app_type] => utility [patent_app_number] => 11/021633 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330054.pdf [firstpage_image] =>[orig_patent_app_number] => 11021633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021633
Leakage efficient anti-glitch filter Dec 22, 2004 Issued
Array ( [id] => 345656 [patent_doc_number] => 07498846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-03 [patent_title] => 'Power efficient multiplexer' [patent_app_type] => utility [patent_app_number] => 11/021632 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498846.pdf [firstpage_image] =>[orig_patent_app_number] => 11021632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021632
Power efficient multiplexer Dec 22, 2004 Issued
Array ( [id] => 196790 [patent_doc_number] => 07635992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-22 [patent_title] => 'Configurable tapered delay chain with multiple sizes of delay elements' [patent_app_type] => utility [patent_app_number] => 11/021222 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635992.pdf [firstpage_image] =>[orig_patent_app_number] => 11021222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021222
Configurable tapered delay chain with multiple sizes of delay elements Dec 22, 2004 Issued
Array ( [id] => 500655 [patent_doc_number] => 07208973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'On die termination circuit' [patent_app_type] => utility [patent_app_number] => 11/008043 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2070 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208973.pdf [firstpage_image] =>[orig_patent_app_number] => 11008043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008043
On die termination circuit Dec 8, 2004 Issued
Array ( [id] => 6916912 [patent_doc_number] => 20050094473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => utility [patent_app_number] => 11/004823 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15476 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094473.pdf [firstpage_image] =>[orig_patent_app_number] => 11004823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/004823
Semiconductor integrated circuits with power reduction mechanism Dec 6, 2004 Issued
Array ( [id] => 398245 [patent_doc_number] => 07295041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Circuits and methods for detecting and assisting wire transitions' [patent_app_type] => utility [patent_app_number] => 11/005762 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295041.pdf [firstpage_image] =>[orig_patent_app_number] => 11005762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005762
Circuits and methods for detecting and assisting wire transitions Dec 5, 2004 Issued
Array ( [id] => 537708 [patent_doc_number] => 07180326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Noise elimination circuit' [patent_app_type] => utility [patent_app_number] => 10/998838 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8639 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180326.pdf [firstpage_image] =>[orig_patent_app_number] => 10998838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998838
Noise elimination circuit Nov 29, 2004 Issued
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