Search

Daniel D. Chang

Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2845, 2819, 2844, 0
Total Applications
2565
Issued Applications
2341
Pending Applications
103
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 488059 [patent_doc_number] => 07218148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Tracking unity gain for edge rate and timing control' [patent_app_type] => utility [patent_app_number] => 10/999781 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4001 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218148.pdf [firstpage_image] =>[orig_patent_app_number] => 10999781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999781
Tracking unity gain for edge rate and timing control Nov 29, 2004 Issued
Array ( [id] => 550564 [patent_doc_number] => 07170313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Apparatus for calibrating termination voltage of on-die termination' [patent_app_type] => utility [patent_app_number] => 10/999500 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2290 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170313.pdf [firstpage_image] =>[orig_patent_app_number] => 10999500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999500
Apparatus for calibrating termination voltage of on-die termination Nov 29, 2004 Issued
Array ( [id] => 492188 [patent_doc_number] => 07215143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Input buffer for multiple differential I/O standards' [patent_app_type] => utility [patent_app_number] => 11/000472 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8921 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215143.pdf [firstpage_image] =>[orig_patent_app_number] => 11000472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000472
Input buffer for multiple differential I/O standards Nov 28, 2004 Issued
Array ( [id] => 504270 [patent_doc_number] => 07205787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'On-chip termination for a high-speed single-ended interface' [patent_app_type] => utility [patent_app_number] => 10/997447 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4840 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205787.pdf [firstpage_image] =>[orig_patent_app_number] => 10997447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997447
On-chip termination for a high-speed single-ended interface Nov 23, 2004 Issued
Array ( [id] => 878021 [patent_doc_number] => 07358760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Efficient 4:1 multiplexer for programmable chips' [patent_app_type] => utility [patent_app_number] => 10/997792 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5703 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358760.pdf [firstpage_image] =>[orig_patent_app_number] => 10997792 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997792
Efficient 4:1 multiplexer for programmable chips Nov 23, 2004 Issued
Array ( [id] => 6956181 [patent_doc_number] => 20050212551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Memory module system with efficient control of on-die termination' [patent_app_type] => utility [patent_app_number] => 10/997406 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7199 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212551.pdf [firstpage_image] =>[orig_patent_app_number] => 10997406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997406
Memory module system with efficient control of on-die termination Nov 23, 2004 Issued
Array ( [id] => 7185116 [patent_doc_number] => 20050162192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal' [patent_app_type] => utility [patent_app_number] => 10/992077 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3120 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162192.pdf [firstpage_image] =>[orig_patent_app_number] => 10992077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992077
Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal Nov 18, 2004 Issued
Array ( [id] => 6936964 [patent_doc_number] => 20050110525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Current-mode logic circuit' [patent_app_type] => utility [patent_app_number] => 10/990431 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7917 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110525.pdf [firstpage_image] =>[orig_patent_app_number] => 10990431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990431
Current-mode logic circuit Nov 17, 2004 Abandoned
Array ( [id] => 480745 [patent_doc_number] => 07224180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Methods and systems for rise-time improvements in differential signal outputs' [patent_app_type] => utility [patent_app_number] => 10/991724 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5471 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224180.pdf [firstpage_image] =>[orig_patent_app_number] => 10991724 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991724
Methods and systems for rise-time improvements in differential signal outputs Nov 17, 2004 Issued
Array ( [id] => 7095487 [patent_doc_number] => 20050127945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Data inversion circuits having a bypass mode of operation and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 10/991076 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21716 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127945.pdf [firstpage_image] =>[orig_patent_app_number] => 10991076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991076
Data inversion circuits having a bypass mode of operation and methods of operating the same Nov 16, 2004 Issued
Array ( [id] => 620615 [patent_doc_number] => 07142014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'High frequency XOR with peaked load stage' [patent_app_type] => utility [patent_app_number] => 10/990047 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7079 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142014.pdf [firstpage_image] =>[orig_patent_app_number] => 10990047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990047
High frequency XOR with peaked load stage Nov 15, 2004 Issued
Array ( [id] => 5774790 [patent_doc_number] => 20060103430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Leakage-tolerant dynamic wide-nor circuit structure' [patent_app_type] => utility [patent_app_number] => 10/990140 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3347 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20060103430.pdf [firstpage_image] =>[orig_patent_app_number] => 10990140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990140
Leakage-tolerant dynamic wide-NOR circuit structure Nov 14, 2004 Issued
Array ( [id] => 589020 [patent_doc_number] => 07446559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method and system for powering an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/576570 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2638 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446559.pdf [firstpage_image] =>[orig_patent_app_number] => 10576570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/576570
Method and system for powering an integrated circuit Oct 17, 2004 Issued
Array ( [id] => 7222403 [patent_doc_number] => 20050077916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Programming circuit and method having extended duration programming capabilities' [patent_app_type] => utility [patent_app_number] => 10/968446 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6070 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077916.pdf [firstpage_image] =>[orig_patent_app_number] => 10968446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/968446
Programming circuit and method having extended duration programming capabilities Oct 17, 2004 Issued
Array ( [id] => 527619 [patent_doc_number] => 07187202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-06 [patent_title] => 'Circuit for reducing programmable logic pin counts for large scale logic' [patent_app_type] => utility [patent_app_number] => 10/956210 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5789 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187202.pdf [firstpage_image] =>[orig_patent_app_number] => 10956210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956210
Circuit for reducing programmable logic pin counts for large scale logic Sep 29, 2004 Issued
Array ( [id] => 5635377 [patent_doc_number] => 20060066350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Equalizing driver circuit and method of operating same' [patent_app_type] => utility [patent_app_number] => 10/949372 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10697 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066350.pdf [firstpage_image] =>[orig_patent_app_number] => 10949372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949372
Equalizing driver circuit and method of operating same Sep 26, 2004 Abandoned
Array ( [id] => 7603027 [patent_doc_number] => 07236007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'Methods and systems for achieving improved intellectual property protection for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/949481 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1608 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236007.pdf [firstpage_image] =>[orig_patent_app_number] => 10949481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949481
Methods and systems for achieving improved intellectual property protection for programmable logic devices Sep 23, 2004 Issued
Array ( [id] => 630893 [patent_doc_number] => 07132854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-07 [patent_title] => 'Data path configurable for multiple clocking arrangements' [patent_app_type] => utility [patent_app_number] => 10/949537 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132854.pdf [firstpage_image] =>[orig_patent_app_number] => 10949537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949537
Data path configurable for multiple clocking arrangements Sep 22, 2004 Issued
Array ( [id] => 531965 [patent_doc_number] => 07183795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Majority voter apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 10/947765 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3228 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183795.pdf [firstpage_image] =>[orig_patent_app_number] => 10947765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947765
Majority voter apparatus, systems, and methods Sep 22, 2004 Issued
Array ( [id] => 7114761 [patent_doc_number] => 20050068062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Semiconductor device and level conversion circuit' [patent_app_type] => utility [patent_app_number] => 10/947257 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13598 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068062.pdf [firstpage_image] =>[orig_patent_app_number] => 10947257 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947257
Semiconductor device and level conversion circuit Sep 22, 2004 Issued
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