
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 488059
[patent_doc_number] => 07218148
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[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Tracking unity gain for edge rate and timing control'
[patent_app_type] => utility
[patent_app_number] => 10/999781
[patent_app_country] => US
[patent_app_date] => 2004-11-30
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[pdf_file] => patents/07/218/07218148.pdf
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Array
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[patent_issue_date] => 2007-01-30
[patent_title] => 'Apparatus for calibrating termination voltage of on-die termination'
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Array
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[patent_issue_date] => 2007-05-08
[patent_title] => 'Input buffer for multiple differential I/O standards'
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[patent_app_number] => 11/000472
[patent_app_country] => US
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Array
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[patent_title] => 'On-chip termination for a high-speed single-ended interface'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/997447 | On-chip termination for a high-speed single-ended interface | Nov 23, 2004 | Issued |
Array
(
[id] => 878021
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[patent_title] => 'Efficient 4:1 multiplexer for programmable chips'
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Array
(
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[patent_title] => 'Memory module system with efficient control of on-die termination'
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Array
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[id] => 7185116
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[patent_title] => 'Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal'
[patent_app_type] => utility
[patent_app_number] => 10/992077
[patent_app_country] => US
[patent_app_date] => 2004-11-19
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/992077 | Multiplex (MUX) circuit having a single selection signal and method of generating a MUX output signal with single selection signal | Nov 18, 2004 | Issued |
Array
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[id] => 6936964
[patent_doc_number] => 20050110525
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[patent_issue_date] => 2005-05-26
[patent_title] => 'Current-mode logic circuit'
[patent_app_type] => utility
[patent_app_number] => 10/990431
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/990431 | Current-mode logic circuit | Nov 17, 2004 | Abandoned |
Array
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[id] => 480745
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991724 | Methods and systems for rise-time improvements in differential signal outputs | Nov 17, 2004 | Issued |
Array
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[patent_title] => 'Data inversion circuits having a bypass mode of operation and methods of operating the same'
[patent_app_type] => utility
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Array
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[id] => 620615
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[patent_title] => 'High frequency XOR with peaked load stage'
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Array
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Array
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[patent_title] => 'Method and system for powering an integrated circuit'
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Array
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Array
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Array
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Array
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