Daniel D. Chang

Array ( [id] => 7221914 [patent_doc_number] => 20040155683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Methods and systems for providing load-adaptive output current drive' [patent_app_type] => new [patent_app_number] => 10/704901 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6218 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155683.pdf [firstpage_image] =>[orig_patent_app_number] => 10704901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 956647 [patent_doc_number] => 06956401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Differential input buffers with elevated power supplies' [patent_app_type] => utility [patent_app_number] => 10/704964 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/956/06956401.pdf [firstpage_image] =>[orig_patent_app_number] => 10704964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6903810 [patent_doc_number] => 20050099205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'REGISTER-FILE BIT-READ METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 10/703016 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20050099205.pdf [firstpage_image] =>[orig_patent_app_number] => 10703016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 677447 [patent_doc_number] => 07088136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Programmable logic device latch circuits' [patent_app_type] => utility [patent_app_number] => 10/702999 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7732 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088136.pdf [firstpage_image] =>[orig_patent_app_number] => 10702999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6916016 [patent_doc_number] => 20050093577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Multiplexer circuits' [patent_app_type] => utility [patent_app_number] => 10/701667 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4545 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093577.pdf [firstpage_image] =>[orig_patent_app_number] => 10701667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 988518 [patent_doc_number] => 06922073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Circuit configuration for signal balancing in antiphase bus drivers' [patent_app_type] => utility [patent_app_number] => 10/698063 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2832 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922073.pdf [firstpage_image] =>[orig_patent_app_number] => 10698063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 793524 [patent_doc_number] => 06982570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Reconfigurable device' [patent_app_type] => utility [patent_app_number] => 10/698271 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 10742 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982570.pdf [firstpage_image] =>[orig_patent_app_number] => 10698271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619601 [patent_doc_number] => 06943585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Input buffer circuit' [patent_app_type] => utility [patent_app_number] => 10/694966 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4010 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943585.pdf [firstpage_image] =>[orig_patent_app_number] => 10694966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7373458 [patent_doc_number] => 20040080338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Bidirectional port with clock channel used for synchronization' [patent_app_type] => new [patent_app_number] => 10/690235 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8444 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080338.pdf [firstpage_image] =>[orig_patent_app_number] => 10690235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7155550 [patent_doc_number] => 20050083081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method and structure for short range leakage control in pipelined circuits' [patent_app_type] => utility [patent_app_number] => 10/685863 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5933 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083081.pdf [firstpage_image] =>[orig_patent_app_number] => 10685863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1060527 [patent_doc_number] => 06853215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Programmable I/O element circuit for high speed logic devices' [patent_app_type] => utility [patent_app_number] => 10/685355 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853215.pdf [firstpage_image] =>[orig_patent_app_number] => 10685355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762547 [patent_doc_number] => 07012448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Integrated circuit and related improvements' [patent_app_type] => utility [patent_app_number] => 10/679978 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 12916 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012448.pdf [firstpage_image] =>[orig_patent_app_number] => 10679978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7115510 [patent_doc_number] => 20050068811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'NON-CASCADING CHARGE PUMP CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 10/675661 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5452 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068811.pdf [firstpage_image] =>[orig_patent_app_number] => 10675661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619604 [patent_doc_number] => 06943582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Programmable I/O structure for FPGAs and the like having shared circuitry' [patent_app_type] => utility [patent_app_number] => 10/671363 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4604 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943582.pdf [firstpage_image] =>[orig_patent_app_number] => 10671363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619603 [patent_doc_number] => 06943583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Programmable I/O structure for FPGAs and the like having reduced pad capacitance' [patent_app_type] => utility [patent_app_number] => 10/671378 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4629 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943583.pdf [firstpage_image] =>[orig_patent_app_number] => 10671378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7607027 [patent_doc_number] => 07098689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Disabling unused/inactive resources in programmable logic devices for static power reduction' [patent_app_type] => utility [patent_app_number] => 10/666669 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3174 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098689.pdf [firstpage_image] =>[orig_patent_app_number] => 10666669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 735059 [patent_doc_number] => 07038490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Delay-matched ASIC conversion of a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/660814 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3575 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038490.pdf [firstpage_image] =>[orig_patent_app_number] => 10660814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7279145 [patent_doc_number] => 20040061522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Digital level shifter with reduced power dissipation and false transmission blocking' [patent_app_type] => new [patent_app_number] => 10/662070 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4683 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061522.pdf [firstpage_image] =>[orig_patent_app_number] => 10662070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 935782 [patent_doc_number] => 06975132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'DAC based driver with selectable pre-emphasis signal levels' [patent_app_type] => utility [patent_app_number] => 10/660062 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8233 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975132.pdf [firstpage_image] =>[orig_patent_app_number] => 10660062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7200275 [patent_doc_number] => 20050052202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Limited switch dynamic logic circuit with keeper' [patent_app_type] => utility [patent_app_number] => 10/655375 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4674 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052202.pdf [firstpage_image] =>[orig_patent_app_number] => 10655375 [rel_patent_id] =>[rel_patent_doc_number] =>)