
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7200277
[patent_doc_number] => 20050052203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'DUO-MODE KEEPER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 10/655376
[patent_app_country] => US
[patent_app_date] => 2003-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4804
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20050052203.pdf
[firstpage_image] =>[orig_patent_app_number] => 10655376
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/655376 | Duo-mode keeper circuit | Sep 3, 2003 | Issued |
Array
(
[id] => 1038166
[patent_doc_number] => 06873184
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-29
[patent_title] => 'Circular buffer using grouping for find first function'
[patent_app_type] => utility
[patent_app_number] => 10/653802
[patent_app_country] => US
[patent_app_date] => 2003-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11037
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/873/06873184.pdf
[firstpage_image] =>[orig_patent_app_number] => 10653802
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653802 | Circular buffer using grouping for find first function | Sep 2, 2003 | Issued |
Array
(
[id] => 893416
[patent_doc_number] => 07345511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-18
[patent_title] => 'Logic circuit and method of logic circuit design'
[patent_app_type] => utility
[patent_app_number] => 10/648474
[patent_app_country] => US
[patent_app_date] => 2003-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 80
[patent_no_of_words] => 20862
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/345/07345511.pdf
[firstpage_image] =>[orig_patent_app_number] => 10648474
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/648474 | Logic circuit and method of logic circuit design | Aug 26, 2003 | Issued |
Array
(
[id] => 470056
[patent_doc_number] => 07233166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-19
[patent_title] => 'Bus state keepers'
[patent_app_type] => utility
[patent_app_number] => 10/649067
[patent_app_country] => US
[patent_app_date] => 2003-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 64
[patent_figures_cnt] => 83
[patent_no_of_words] => 52711
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/233/07233166.pdf
[firstpage_image] =>[orig_patent_app_number] => 10649067
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/649067 | Bus state keepers | Aug 26, 2003 | Issued |
Array
(
[id] => 7270925
[patent_doc_number] => 20040059443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata'
[patent_app_type] => new
[patent_app_number] => 10/650364
[patent_app_country] => US
[patent_app_date] => 2003-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8449
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20040059443.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650364
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650364 | Method and apparatus for efficient implementation and evaluation of state machines and programmable finite state automata | Aug 26, 2003 | Issued |
Array
(
[id] => 775081
[patent_doc_number] => 07002366
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Superconducting constant current source'
[patent_app_type] => utility
[patent_app_number] => 10/644461
[patent_app_country] => US
[patent_app_date] => 2003-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4586
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/002/07002366.pdf
[firstpage_image] =>[orig_patent_app_number] => 10644461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/644461 | Superconducting constant current source | Aug 19, 2003 | Issued |
Array
(
[id] => 1055889
[patent_doc_number] => 06859917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-22
[patent_title] => 'Semiconductor integrated circuit having high-speed and low-power logic gates with common transistor substrate potentials, design methods thereof, and related program recording medium'
[patent_app_type] => utility
[patent_app_number] => 10/641109
[patent_app_country] => US
[patent_app_date] => 2003-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 40
[patent_no_of_words] => 15605
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/859/06859917.pdf
[firstpage_image] =>[orig_patent_app_number] => 10641109
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/641109 | Semiconductor integrated circuit having high-speed and low-power logic gates with common transistor substrate potentials, design methods thereof, and related program recording medium | Aug 14, 2003 | Issued |
Array
(
[id] => 6970073
[patent_doc_number] => 20050035783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 10/642370
[patent_app_country] => US
[patent_app_date] => 2003-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3755
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20050035783.pdf
[firstpage_image] =>[orig_patent_app_number] => 10642370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/642370 | Field programmable gate array | Aug 14, 2003 | Issued |
Array
(
[id] => 7315948
[patent_doc_number] => 20040034681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-19
[patent_title] => 'Non-inverting domino register'
[patent_app_type] => new
[patent_app_number] => 10/640369
[patent_app_country] => US
[patent_app_date] => 2003-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4750
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20040034681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10640369
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640369 | Non-inverting domino register | Aug 12, 2003 | Issued |
Array
(
[id] => 6973907
[patent_doc_number] => 20050039039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Method and apparatus for providing security for debug circuitry'
[patent_app_type] => utility
[patent_app_number] => 10/638795
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3996
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20050039039.pdf
[firstpage_image] =>[orig_patent_app_number] => 10638795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/638795 | Method and apparatus for providing security for debug circuitry | Aug 10, 2003 | Issued |
Array
(
[id] => 7292404
[patent_doc_number] => 20040212407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Semiconductor integrated circuit having system bus divided in stages'
[patent_app_type] => new
[patent_app_number] => 10/632866
[patent_app_country] => US
[patent_app_date] => 2003-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6555
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20040212407.pdf
[firstpage_image] =>[orig_patent_app_number] => 10632866
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/632866 | Semiconductor integrated circuit having system bus divided in stages | Aug 3, 2003 | Issued |
Array
(
[id] => 1009901
[patent_doc_number] => 06900665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Transfer of digital data across asynchronous clock domains'
[patent_app_type] => utility
[patent_app_number] => 10/630543
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4240
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/900/06900665.pdf
[firstpage_image] =>[orig_patent_app_number] => 10630543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/630543 | Transfer of digital data across asynchronous clock domains | Jul 28, 2003 | Issued |
Array
(
[id] => 1121545
[patent_doc_number] => 06798243
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-28
[patent_title] => 'Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage'
[patent_app_type] => B1
[patent_app_number] => 10/629167
[patent_app_country] => US
[patent_app_date] => 2003-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6423
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/798/06798243.pdf
[firstpage_image] =>[orig_patent_app_number] => 10629167
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/629167 | Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage | Jul 27, 2003 | Issued |
Array
(
[id] => 1074235
[patent_doc_number] => 06838901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-04
[patent_title] => 'Semiconductor integrated circuits with power reduction mechanism'
[patent_app_type] => utility
[patent_app_number] => 10/626532
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 15687
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/838/06838901.pdf
[firstpage_image] =>[orig_patent_app_number] => 10626532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626532 | Semiconductor integrated circuits with power reduction mechanism | Jul 24, 2003 | Issued |
Array
(
[id] => 7222605
[patent_doc_number] => 20050077944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Linear buffer'
[patent_app_type] => utility
[patent_app_number] => 10/626701
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6950
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077944.pdf
[firstpage_image] =>[orig_patent_app_number] => 10626701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626701 | Linear buffer | Jul 24, 2003 | Issued |
Array
(
[id] => 969031
[patent_doc_number] => 06940309
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-06
[patent_title] => 'Programmable logic device with a memory-based finite state machine'
[patent_app_type] => utility
[patent_app_number] => 10/624965
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4029
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/940/06940309.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624965
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624965 | Programmable logic device with a memory-based finite state machine | Jul 20, 2003 | Issued |
Array
(
[id] => 7621978
[patent_doc_number] => 06977523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => 'Voltage level shifting circuit'
[patent_app_type] => utility
[patent_app_number] => 10/621368
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5518
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 405
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977523.pdf
[firstpage_image] =>[orig_patent_app_number] => 10621368
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/621368 | Voltage level shifting circuit | Jul 17, 2003 | Issued |
Array
(
[id] => 954210
[patent_doc_number] => 06958625
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-10-25
[patent_title] => 'Programmable logic device with hardwired microsequencer'
[patent_app_type] => utility
[patent_app_number] => 10/617980
[patent_app_country] => US
[patent_app_date] => 2003-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2708
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/958/06958625.pdf
[firstpage_image] =>[orig_patent_app_number] => 10617980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617980 | Programmable logic device with hardwired microsequencer | Jul 9, 2003 | Issued |
Array
(
[id] => 1015297
[patent_doc_number] => 06894529
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-17
[patent_title] => 'Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control'
[patent_app_type] => utility
[patent_app_number] => 10/616272
[patent_app_country] => US
[patent_app_date] => 2003-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6360
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/894/06894529.pdf
[firstpage_image] =>[orig_patent_app_number] => 10616272
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/616272 | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control | Jul 8, 2003 | Issued |
Array
(
[id] => 956651
[patent_doc_number] => 06956405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'Teacher-pupil flip-flop'
[patent_app_type] => utility
[patent_app_number] => 10/616473
[patent_app_country] => US
[patent_app_date] => 2003-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7340
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/956/06956405.pdf
[firstpage_image] =>[orig_patent_app_number] => 10616473
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/616473 | Teacher-pupil flip-flop | Jul 8, 2003 | Issued |