
Daniel D. Chang
Examiner (ID: 461, Phone: (571)272-1801 , Office: P/2844 )
| Most Active Art Unit | 2844 |
| Art Unit(s) | 2845, 2819, 2844, 0 |
| Total Applications | 2565 |
| Issued Applications | 2341 |
| Pending Applications | 103 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7423765
[patent_doc_number] => 20040183568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Level-shifting circuit'
[patent_app_type] => new
[patent_app_number] => 10/615464
[patent_app_country] => US
[patent_app_date] => 2003-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2774
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20040183568.pdf
[firstpage_image] =>[orig_patent_app_number] => 10615464
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/615464 | Level-shifting circuit | Jul 6, 2003 | Issued |
Array
(
[id] => 961402
[patent_doc_number] => 06952115
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-10-04
[patent_title] => 'Programmable I/O interfaces for FPGAs and other PLDs'
[patent_app_type] => utility
[patent_app_number] => 10/613462
[patent_app_country] => US
[patent_app_date] => 2003-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11057
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/952/06952115.pdf
[firstpage_image] =>[orig_patent_app_number] => 10613462
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/613462 | Programmable I/O interfaces for FPGAs and other PLDs | Jul 2, 2003 | Issued |
Array
(
[id] => 7059290
[patent_doc_number] => 20050001649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'INFORMATION HANDLING SYSTEM INCLUDING A BUS IN WHICH IMPEDANCE DISCONTINUITIES ASSOCIATED WITH MULTIPLE EXPANSION CONNECTORS ARE REDUCED'
[patent_app_type] => utility
[patent_app_number] => 10/614578
[patent_app_country] => US
[patent_app_date] => 2003-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3509
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20050001649.pdf
[firstpage_image] =>[orig_patent_app_number] => 10614578
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/614578 | Information handling system including a bus in which impedance discontinuities associated with multiple expansion connectors are reduced | Jul 2, 2003 | Issued |
Array
(
[id] => 1035443
[patent_doc_number] => 06876230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-05
[patent_title] => 'Synchronous clocked full-rail differential logic with single-rail logic and shut-off'
[patent_app_type] => utility
[patent_app_number] => 10/611266
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5913
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 843
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/876/06876230.pdf
[firstpage_image] =>[orig_patent_app_number] => 10611266
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/611266 | Synchronous clocked full-rail differential logic with single-rail logic and shut-off | Jun 29, 2003 | Issued |
Array
(
[id] => 6989925
[patent_doc_number] => 20050088962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Digital filter circuit and method for blocking a transmission line reflection signal'
[patent_app_type] => utility
[patent_app_number] => 10/610274
[patent_app_country] => US
[patent_app_date] => 2003-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4331
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20050088962.pdf
[firstpage_image] =>[orig_patent_app_number] => 10610274
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/610274 | Digital filter circuit and method for blocking a transmission line reflection signal | Jun 29, 2003 | Issued |
Array
(
[id] => 7612258
[patent_doc_number] => 06903579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Pipelined low-voltage current-mode logic with a switching stack height of one'
[patent_app_type] => utility
[patent_app_number] => 10/607468
[patent_app_country] => US
[patent_app_date] => 2003-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2271
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/903/06903579.pdf
[firstpage_image] =>[orig_patent_app_number] => 10607468
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/607468 | Pipelined low-voltage current-mode logic with a switching stack height of one | Jun 25, 2003 | Issued |
Array
(
[id] => 7305451
[patent_doc_number] => 20040140827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Output circuit of semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/465871
[patent_app_country] => US
[patent_app_date] => 2003-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4099
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20040140827.pdf
[firstpage_image] =>[orig_patent_app_number] => 10465871
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/465871 | Output circuit of semiconductor integrated circuit device | Jun 19, 2003 | Issued |
Array
(
[id] => 938809
[patent_doc_number] => 06972638
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-06
[patent_title] => 'Directional coupler and electronic device using the same'
[patent_app_type] => utility
[patent_app_number] => 10/463447
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 4193
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/972/06972638.pdf
[firstpage_image] =>[orig_patent_app_number] => 10463447
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/463447 | Directional coupler and electronic device using the same | Jun 17, 2003 | Issued |
Array
(
[id] => 7238672
[patent_doc_number] => 20040257170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Improved switching system for broadcast transmission'
[patent_app_type] => new
[patent_app_number] => 10/463514
[patent_app_country] => US
[patent_app_date] => 2003-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4218
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20040257170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10463514
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/463514 | Switching system for broadcast transmission | Jun 17, 2003 | Issued |
Array
(
[id] => 961431
[patent_doc_number] => 06952144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-04
[patent_title] => 'Apparatus and method to provide power amplification'
[patent_app_type] => utility
[patent_app_number] => 10/463725
[patent_app_country] => US
[patent_app_date] => 2003-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1919
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/952/06952144.pdf
[firstpage_image] =>[orig_patent_app_number] => 10463725
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/463725 | Apparatus and method to provide power amplification | Jun 15, 2003 | Issued |
Array
(
[id] => 7388167
[patent_doc_number] => 20040021530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'Surface acoustic wave device'
[patent_app_type] => new
[patent_app_number] => 10/460299
[patent_app_country] => US
[patent_app_date] => 2003-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5176
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20040021530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10460299
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/460299 | Surface acoustic wave device | Jun 12, 2003 | Issued |
Array
(
[id] => 7457931
[patent_doc_number] => 20040010726
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Inter-block interface circuit and system LSI'
[patent_app_type] => new
[patent_app_number] => 10/460175
[patent_app_country] => US
[patent_app_date] => 2003-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5306
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20040010726.pdf
[firstpage_image] =>[orig_patent_app_number] => 10460175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/460175 | Inter-block interface circuit and system LSI | Jun 12, 2003 | Issued |
Array
(
[id] => 6803692
[patent_doc_number] => 20030231086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Dielectric resonator and high frequency circuit element using the same'
[patent_app_type] => new
[patent_app_number] => 10/459618
[patent_app_country] => US
[patent_app_date] => 2003-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10831
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20030231086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10459618
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/459618 | Dielectric resonator and high frequency circuit element using the same | Jun 11, 2003 | Abandoned |
Array
(
[id] => 1003033
[patent_doc_number] => 06909339
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-21
[patent_title] => 'Mounting structure of dielectric filter, dielectric filter device, mounting structure of dielectric duplexer, and communication device'
[patent_app_type] => utility
[patent_app_number] => 10/459673
[patent_app_country] => US
[patent_app_date] => 2003-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 5302
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/909/06909339.pdf
[firstpage_image] =>[orig_patent_app_number] => 10459673
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/459673 | Mounting structure of dielectric filter, dielectric filter device, mounting structure of dielectric duplexer, and communication device | Jun 11, 2003 | Issued |
Array
(
[id] => 1044572
[patent_doc_number] => 06867663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-15
[patent_title] => 'Dielectric duplexer'
[patent_app_type] => utility
[patent_app_number] => 10/457536
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 4391
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/867/06867663.pdf
[firstpage_image] =>[orig_patent_app_number] => 10457536
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/457536 | Dielectric duplexer | Jun 9, 2003 | Issued |
Array
(
[id] => 7286963
[patent_doc_number] => 20040108872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'VOLTAGE-CONTROLLED DELAY LINE WITH REDUCED TIMING ERRORS AND JITTERS'
[patent_app_type] => new
[patent_app_number] => 10/250171
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6349
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 387
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20040108872.pdf
[firstpage_image] =>[orig_patent_app_number] => 10250171
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/250171 | Voltage-controlled delay line with reduced timing errors and jitters | Jun 9, 2003 | Issued |
Array
(
[id] => 994156
[patent_doc_number] => 06917257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-12
[patent_title] => 'Apparatus and method for equalizing received signals'
[patent_app_type] => utility
[patent_app_number] => 10/458519
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4612
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/917/06917257.pdf
[firstpage_image] =>[orig_patent_app_number] => 10458519
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458519 | Apparatus and method for equalizing received signals | Jun 9, 2003 | Issued |
Array
(
[id] => 1006370
[patent_doc_number] => 06906555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Prevention of metastability in bistable circuits'
[patent_app_type] => utility
[patent_app_number] => 10/458878
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4823
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/906/06906555.pdf
[firstpage_image] =>[orig_patent_app_number] => 10458878
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458878 | Prevention of metastability in bistable circuits | Jun 9, 2003 | Issued |
Array
(
[id] => 982803
[patent_doc_number] => 06927647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-09
[patent_title] => 'Two channels, high speed, RF switch'
[patent_app_type] => utility
[patent_app_number] => 10/458762
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2228
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/927/06927647.pdf
[firstpage_image] =>[orig_patent_app_number] => 10458762
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458762 | Two channels, high speed, RF switch | Jun 9, 2003 | Issued |
Array
(
[id] => 7339830
[patent_doc_number] => 20040246067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'High isolation switch in balanced lines'
[patent_app_type] => new
[patent_app_number] => 10/458538
[patent_app_country] => US
[patent_app_date] => 2003-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2327
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20040246067.pdf
[firstpage_image] =>[orig_patent_app_number] => 10458538
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/458538 | High isolation switch in balanced lines | Jun 8, 2003 | Issued |