Search

Daniel D. Lowrey

Examiner (ID: 12333, Phone: (571)270-1455 , Office: P/1787 )

Most Active Art Unit
1787
Art Unit(s)
1787
Total Applications
199
Issued Applications
33
Pending Applications
0
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3522013 [patent_doc_number] => 05588152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Advanced parallel processor including advanced support hardware' [patent_app_type] => 1 [patent_app_number] => 8/519859 [patent_app_country] => US [patent_app_date] => 1995-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 39703 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588152.pdf [firstpage_image] =>[orig_patent_app_number] => 519859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519859
Advanced parallel processor including advanced support hardware Aug 24, 1995 Issued
Array ( [id] => 3758707 [patent_doc_number] => 05754829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Parallel computer system operating method employing a manager node to distribute attributes of individual servers' [patent_app_type] => 1 [patent_app_number] => 8/518976 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4131 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754829.pdf [firstpage_image] =>[orig_patent_app_number] => 518976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/518976
Parallel computer system operating method employing a manager node to distribute attributes of individual servers Aug 23, 1995 Issued
Array ( [id] => 3712362 [patent_doc_number] => 05675502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Estimating propagation delays in a programmable device' [patent_app_type] => 1 [patent_app_number] => 8/517871 [patent_app_country] => US [patent_app_date] => 1995-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5203 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675502.pdf [firstpage_image] =>[orig_patent_app_number] => 517871 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517871
Estimating propagation delays in a programmable device Aug 21, 1995 Issued
Array ( [id] => 3758644 [patent_doc_number] => 05754826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'CAD and simulation system for targeting IC designs to multiple fabrication processes' [patent_app_type] => 1 [patent_app_number] => 8/511172 [patent_app_country] => US [patent_app_date] => 1995-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754826.pdf [firstpage_image] =>[orig_patent_app_number] => 511172 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/511172
CAD and simulation system for targeting IC designs to multiple fabrication processes Aug 3, 1995 Issued
Array ( [id] => 3939391 [patent_doc_number] => 05877958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Apparatus for controlling an automobile engine which is serially connected to system sensors' [patent_app_type] => 1 [patent_app_number] => 8/511046 [patent_app_country] => US [patent_app_date] => 1995-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 52 [patent_no_of_words] => 4095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877958.pdf [firstpage_image] =>[orig_patent_app_number] => 511046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/511046
Apparatus for controlling an automobile engine which is serially connected to system sensors Aug 2, 1995 Issued
Array ( [id] => 3853188 [patent_doc_number] => 05745374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Layout method for semiconductor integrated circuit and layout apparatus for semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/505735 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4806 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745374.pdf [firstpage_image] =>[orig_patent_app_number] => 505735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505735
Layout method for semiconductor integrated circuit and layout apparatus for semiconductor integrated circuit Jul 20, 1995 Issued
Array ( [id] => 3968592 [patent_doc_number] => 05978575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Remote terminal emulator with improved time accounting' [patent_app_type] => 1 [patent_app_number] => 8/499186 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8555 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978575.pdf [firstpage_image] =>[orig_patent_app_number] => 499186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499186
Remote terminal emulator with improved time accounting Jul 6, 1995 Issued
Array ( [id] => 3673484 [patent_doc_number] => 05649170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Interconnect and driver optimization for high performance processors' [patent_app_type] => 1 [patent_app_number] => 8/497175 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2875 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649170.pdf [firstpage_image] =>[orig_patent_app_number] => 497175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497175
Interconnect and driver optimization for high performance processors Jun 29, 1995 Issued
Array ( [id] => 3824958 [patent_doc_number] => 05710908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Adaptive network protocol independent interface' [patent_app_type] => 1 [patent_app_number] => 8/495172 [patent_app_country] => US [patent_app_date] => 1995-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8218 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710908.pdf [firstpage_image] =>[orig_patent_app_number] => 495172 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/495172
Adaptive network protocol independent interface Jun 26, 1995 Issued
Array ( [id] => 3671860 [patent_doc_number] => 05625559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Transport management control apparatus and method for unmanned vehicle system' [patent_app_type] => 1 [patent_app_number] => 8/493783 [patent_app_country] => US [patent_app_date] => 1995-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 75 [patent_no_of_words] => 14923 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625559.pdf [firstpage_image] =>[orig_patent_app_number] => 493783 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493783
Transport management control apparatus and method for unmanned vehicle system Jun 21, 1995 Issued
Array ( [id] => 3888892 [patent_doc_number] => 05825659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method for local rip-up and reroute of signal paths in an IC design' [patent_app_type] => 1 [patent_app_number] => 8/491433 [patent_app_country] => US [patent_app_date] => 1995-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4536 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825659.pdf [firstpage_image] =>[orig_patent_app_number] => 491433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491433
Method for local rip-up and reroute of signal paths in an IC design Jun 15, 1995 Issued
Array ( [id] => 3813199 [patent_doc_number] => 05828863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer' [patent_app_type] => 1 [patent_app_number] => 8/489282 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 23077 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828863.pdf [firstpage_image] =>[orig_patent_app_number] => 489282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489282
Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer Jun 8, 1995 Issued
Array ( [id] => 3813237 [patent_doc_number] => 05828864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Network board which responds to status changes of an installed peripheral by generating a testpage' [patent_app_type] => 1 [patent_app_number] => 8/489283 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 23623 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828864.pdf [firstpage_image] =>[orig_patent_app_number] => 489283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489283
Network board which responds to status changes of an installed peripheral by generating a testpage Jun 8, 1995 Issued
Array ( [id] => 3673445 [patent_doc_number] => 05649167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Methods for controlling timing in a logic emulation system' [patent_app_type] => 1 [patent_app_number] => 8/472531 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 10844 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649167.pdf [firstpage_image] =>[orig_patent_app_number] => 472531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472531
Methods for controlling timing in a logic emulation system Jun 6, 1995 Issued
Array ( [id] => 3708487 [patent_doc_number] => 05680621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'System and method for domained incremental changes storage and retrieval' [patent_app_type] => 1 [patent_app_number] => 8/486485 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4341 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680621.pdf [firstpage_image] =>[orig_patent_app_number] => 486485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486485
System and method for domained incremental changes storage and retrieval Jun 6, 1995 Issued
Array ( [id] => 3871223 [patent_doc_number] => 05706476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method and apparatus for use of the undefined logic state and mixed multiple-state abstractions in digital logic simulation' [patent_app_type] => 1 [patent_app_number] => 8/464390 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706476.pdf [firstpage_image] =>[orig_patent_app_number] => 464390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/464390
Method and apparatus for use of the undefined logic state and mixed multiple-state abstractions in digital logic simulation Jun 4, 1995 Issued
Array ( [id] => 3709098 [patent_doc_number] => 05678031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method of testing interconnections of an LSI on a simulator through the use of effective pulse widths' [patent_app_type] => 1 [patent_app_number] => 8/457576 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4996 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678031.pdf [firstpage_image] =>[orig_patent_app_number] => 457576 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/457576
Method of testing interconnections of an LSI on a simulator through the use of effective pulse widths May 31, 1995 Issued
Array ( [id] => 3871188 [patent_doc_number] => 05706474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Synchronous memory system with asynchronous internal memory operation' [patent_app_type] => 1 [patent_app_number] => 8/455155 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 14694 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706474.pdf [firstpage_image] =>[orig_patent_app_number] => 455155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455155
Synchronous memory system with asynchronous internal memory operation May 30, 1995 Issued
Array ( [id] => 3744292 [patent_doc_number] => 05636370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter' [patent_app_type] => 1 [patent_app_number] => 8/454448 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10319 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636370.pdf [firstpage_image] =>[orig_patent_app_number] => 454448 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/454448
System and method for interfacing risc busses to peripheral circuits using another template of busses in a data communication adapter May 29, 1995 Issued
Array ( [id] => 3736032 [patent_doc_number] => 05673419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Parity bit emulator with write parity bit checking' [patent_app_type] => 1 [patent_app_number] => 8/444963 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673419.pdf [firstpage_image] =>[orig_patent_app_number] => 444963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444963
Parity bit emulator with write parity bit checking May 18, 1995 Issued
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