Search

Daniel D. Tsui

Examiner (ID: 18943, Phone: (571)270-3253 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2185, 2132
Total Applications
736
Issued Applications
642
Pending Applications
53
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20520183 [patent_doc_number] => 20260044289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => SYSTEM AND METHOD FOR DATA MANAGEMENT WITH ADAPTIVE RAID IN STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 19/236052 [patent_app_country] => US [patent_app_date] => 2025-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19236052 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/236052
SYSTEM AND METHOD FOR DATA MANAGEMENT WITH ADAPTIVE RAID IN STORAGE DEVICES Jun 11, 2025 Pending
Array ( [id] => 20421903 [patent_doc_number] => 20250383988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => SYSTEMS FOR SOFTWARE OPTIMIZATION OF DATA LAYOUT [patent_app_type] => utility [patent_app_number] => 19/219837 [patent_app_country] => US [patent_app_date] => 2025-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19219837 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/219837
SYSTEMS FOR SOFTWARE OPTIMIZATION OF DATA LAYOUT May 26, 2025 Pending
Array ( [id] => 20208619 [patent_doc_number] => 20250278339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => BACK UP AND RESTORE RELATED DATA ON DIFFERENT CLOUD STORAGE TIERS [patent_app_type] => utility [patent_app_number] => 19/212077 [patent_app_country] => US [patent_app_date] => 2025-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19212077 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/212077
BACK UP AND RESTORE RELATED DATA ON DIFFERENT CLOUD STORAGE TIERS May 18, 2025 Pending
Array ( [id] => 20195530 [patent_doc_number] => 20250272240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY CONTROLLER, STORAGE DEVICE INCLUDING THE MEMORY CONTROLLER, AND METHOD OF OPERATING THE MEMORY CONTROLLER AND THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 19/208402 [patent_app_country] => US [patent_app_date] => 2025-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19208402 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/208402
MEMORY CONTROLLER, STORAGE DEVICE INCLUDING THE MEMORY CONTROLLER, AND METHOD OF OPERATING THE MEMORY CONTROLLER AND THE STORAGE DEVICE May 13, 2025 Pending
Array ( [id] => 20181040 [patent_doc_number] => 20250264998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY MANAGEMENT METHOD AND COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 19/197631 [patent_app_country] => US [patent_app_date] => 2025-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19197631 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/197631
MEMORY MANAGEMENT METHOD AND COMPUTING DEVICE May 1, 2025 Pending
Array ( [id] => 20152024 [patent_doc_number] => 20250251862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/184994 [patent_app_country] => US [patent_app_date] => 2025-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19184994 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/184994
REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS Apr 20, 2025 Pending
Array ( [id] => 20123335 [patent_doc_number] => 20250238366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SOLID-STATE DRIVE CONFIGURATION METHOD, GARBAGE COLLECTION METHOD, AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 19/175747 [patent_app_country] => US [patent_app_date] => 2025-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19175747 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/175747
SOLID-STATE DRIVE CONFIGURATION METHOD, GARBAGE COLLECTION METHOD, AND RELATED DEVICE Apr 9, 2025 Pending
Array ( [id] => 20166555 [patent_doc_number] => 20250258602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => OPERATION TO ERASE MULTIPLE MEMORY BLOCKS OF MULTIPLE MEMORY PLANES [patent_app_type] => utility [patent_app_number] => 19/097330 [patent_app_country] => US [patent_app_date] => 2025-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19097330 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/097330
OPERATION TO ERASE MULTIPLE MEMORY BLOCKS OF MULTIPLE MEMORY PLANES Mar 31, 2025 Pending
Array ( [id] => 20087366 [patent_doc_number] => 20250217302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Adaptive Configuration of Address Translation Cache [patent_app_type] => utility [patent_app_number] => 19/087520 [patent_app_country] => US [patent_app_date] => 2025-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19087520 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/087520
Adaptive Configuration of Address Translation Cache Mar 22, 2025 Pending
Array ( [id] => 20659083 [patent_doc_number] => 20260111126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => MEMORY CIRCUITS WITH HIGH SECURITY AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 19/081550 [patent_app_country] => US [patent_app_date] => 2025-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19081550 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/081550
MEMORY CIRCUITS WITH HIGH SECURITY AND METHODS FOR OPERATING THE SAME Mar 16, 2025 Pending
Array ( [id] => 20221488 [patent_doc_number] => 20250284419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => POWER CYCLE DURATION BASED MEMORY INITIALIZATION [patent_app_type] => utility [patent_app_number] => 19/072804 [patent_app_country] => US [patent_app_date] => 2025-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072804 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/072804
POWER CYCLE DURATION BASED MEMORY INITIALIZATION Mar 5, 2025 Pending
Array ( [id] => 20296636 [patent_doc_number] => 20250321879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => ENHANCED MECHANISM FOR PARTITIONING ADDRESS SPACES [patent_app_type] => utility [patent_app_number] => 19/065855 [patent_app_country] => US [patent_app_date] => 2025-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19065855 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/065855
ENHANCED MECHANISM FOR PARTITIONING ADDRESS SPACES Feb 26, 2025 Pending
Array ( [id] => 20017874 [patent_doc_number] => 20250156096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => OPTIMIZING DATA DEDUPLICATION BY SELECTING BETWEEN MUTLIPLE DEDUPLICATION PROCESSES [patent_app_type] => utility [patent_app_number] => 19/026235 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19026235 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/026235
OPTIMIZING DATA DEDUPLICATION BY SELECTING BETWEEN MUTLIPLE DEDUPLICATION PROCESSES Jan 15, 2025 Pending
Array ( [id] => 20094942 [patent_doc_number] => 20250224878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => QUALITY OF SERVICE MANAGEMENT MECHANISM [patent_app_type] => utility [patent_app_number] => 19/013447 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013447 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013447
QUALITY OF SERVICE MANAGEMENT MECHANISM Jan 7, 2025 Pending
Array ( [id] => 20009481 [patent_doc_number] => 20250147703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => STORAGE SYSTEM AND MEMORY CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 19/013607 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013607 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013607
STORAGE SYSTEM AND MEMORY CONTROL METHOD Jan 7, 2025 Pending
Array ( [id] => 20811843 [patent_doc_number] => 20260186668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-07-02 [patent_title] => Bit Flipping Decoder Threshold Controlling for Error Correction in Memory Devices [patent_app_type] => utility [patent_app_number] => 19/002488 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002488 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002488
Bit Flipping Decoder Threshold Controlling for Error Correction in Memory Devices Dec 25, 2024 Pending
Array ( [id] => 20087132 [patent_doc_number] => 20250217068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => METHOD FOR WRITING TEST PARAMETERS TO BOARD MEMORIES [patent_app_type] => utility [patent_app_number] => 19/000790 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000790 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/000790
METHOD FOR WRITING TEST PARAMETERS TO BOARD MEMORIES Dec 23, 2024 Pending
Array ( [id] => 19864450 [patent_doc_number] => 20250103236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SYSTEMS AND METHODS FOR DATA COPY OFFLOAD FOR STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/973896 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973896
SYSTEMS AND METHODS FOR DATA COPY OFFLOAD FOR STORAGE DEVICES Dec 8, 2024 Pending
Array ( [id] => 20790030 [patent_doc_number] => 12663945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Managing queue limits for data storage device adapters using controller memory buffers [patent_app_type] => utility [patent_app_number] => 18/970077 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970077
Managing queue limits for data storage device adapters using controller memory buffers Dec 4, 2024 Issued
Array ( [id] => 19848712 [patent_doc_number] => 20250094063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE [patent_app_type] => utility [patent_app_number] => 18/968924 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968924
CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE Dec 3, 2024 Issued
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