Search

Daniel D. Tsui

Examiner (ID: 9882, Phone: (571)270-3253 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2132, 2182, 2185
Total Applications
717
Issued Applications
630
Pending Applications
46
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14267271 [patent_doc_number] => 10283205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Preemptive idle time read scans [patent_app_type] => utility [patent_app_number] => 15/571232 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17184 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571232 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571232
Preemptive idle time read scans Sep 29, 2017 Issued
Array ( [id] => 14107363 [patent_doc_number] => 20190095357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => HARDWARE SUPPORT FOR STATIC MODE OF PROTECTED MEMORY MANAGEMENT ON FLEXIBLY-CONVERTIBLE ENCLAVE PLATFORM [patent_app_type] => utility [patent_app_number] => 15/719222 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719222
HARDWARE SUPPORT FOR STATIC MODE OF PROTECTED MEMORY MANAGEMENT ON FLEXIBLY-CONVERTIBLE ENCLAVE PLATFORM Sep 27, 2017 Abandoned
Array ( [id] => 15486427 [patent_doc_number] => 10558564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Pointers in a memory managed system [patent_app_type] => utility [patent_app_number] => 15/719297 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719297 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719297
Pointers in a memory managed system Sep 27, 2017 Issued
Array ( [id] => 14798649 [patent_doc_number] => 10402329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Reducing traffic in hierarchical cache interconnects [patent_app_type] => utility [patent_app_number] => 15/716376 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 14258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716376
Reducing traffic in hierarchical cache interconnects Sep 25, 2017 Issued
Array ( [id] => 15231867 [patent_doc_number] => 10503656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Performance by retaining high locality data in higher level cache memory [patent_app_type] => utility [patent_app_number] => 15/709884 [patent_app_country] => US [patent_app_date] => 2017-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 23801 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709884
Performance by retaining high locality data in higher level cache memory Sep 19, 2017 Issued
Array ( [id] => 12221612 [patent_doc_number] => 20180059972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'POWER EFFICIENT METHOD AND SYSTEM FOR EXECUTING HOST DATA PROCESSING TASKS DURING DATA RETENTION OPERATIONS IN A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/694521 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6447 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694521
Power efficient method and system for executing host data processing tasks during data retention operations in a storage device Aug 31, 2017 Issued
Array ( [id] => 13991903 [patent_doc_number] => 20190065109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHODS OF SYNCHRONIZING MEMORY OPERATIONS AND MEMORY SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 15/693128 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693128 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693128
Methods of synchronizing memory operations and memory systems employing the same Aug 30, 2017 Issued
Array ( [id] => 13991899 [patent_doc_number] => 20190065107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MEMORY DEVICES WITH PROGRAMMABLE LATENCIES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/693095 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693095
Memory devices with programmable latencies and methods for operating the same Aug 30, 2017 Issued
Array ( [id] => 14523627 [patent_doc_number] => 10339075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Clock tree structure in a memory system [patent_app_type] => utility [patent_app_number] => 15/693027 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693027
Clock tree structure in a memory system Aug 30, 2017 Issued
Array ( [id] => 14009601 [patent_doc_number] => 10223259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Memory device with dynamic storage mode control [patent_app_type] => utility [patent_app_number] => 15/693153 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9312 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693153
Memory device with dynamic storage mode control Aug 30, 2017 Issued
Array ( [id] => 13797083 [patent_doc_number] => 20190012080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/690286 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690286
Memory management method, memory control circuit unit and memory storage device Aug 29, 2017 Issued
Array ( [id] => 12094521 [patent_doc_number] => 20170351614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'NON-VOLATILE MEMORY CONTROLLER CACHE ARCHITECTURE WITH SUPPORT FOR SEPARATION OF DATA STREAMS' [patent_app_type] => utility [patent_app_number] => 15/683584 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683584
Non-volatile memory controller cache architecture with support for separation of data streams Aug 21, 2017 Issued
Array ( [id] => 12985738 [patent_doc_number] => 20170344271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => WRITING DATA SPANNING PLURALITY OF TAPE CARTRIDGES [patent_app_type] => utility [patent_app_number] => 15/667940 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667940
Writing data spanning plurality of tape cartridges Aug 2, 2017 Issued
Array ( [id] => 12025812 [patent_doc_number] => 20170315911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'System and Method for Performance Optimal Partial Rank/Bank Interleaving for Non-Symmetrically Populated DIMMs Across DDR Channels' [patent_app_type] => utility [patent_app_number] => 15/654274 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654274
System and method for performance optimal partial rank/bank interleaving for non-symmetrically populated DIMMs across DDR channels Jul 18, 2017 Issued
Array ( [id] => 14982687 [patent_doc_number] => 10445255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => System and method for providing kernel intrusion prevention and notification [patent_app_type] => utility [patent_app_number] => 15/634992 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634992 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634992
System and method for providing kernel intrusion prevention and notification Jun 26, 2017 Issued
Array ( [id] => 13738351 [patent_doc_number] => 20180373645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => PROCESSING CACHE MISS RATES TO DETERMINE MEMORY SPACE TO ADD TO AN ACTIVE CACHE TO REDUCE A CACHE MISS RATE FOR THE ACTIVE CACHE [patent_app_type] => utility [patent_app_number] => 15/629249 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629249
Processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache Jun 20, 2017 Issued
Array ( [id] => 13738351 [patent_doc_number] => 20180373645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => PROCESSING CACHE MISS RATES TO DETERMINE MEMORY SPACE TO ADD TO AN ACTIVE CACHE TO REDUCE A CACHE MISS RATE FOR THE ACTIVE CACHE [patent_app_type] => utility [patent_app_number] => 15/629249 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629249
Processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache Jun 20, 2017 Issued
Array ( [id] => 13738351 [patent_doc_number] => 20180373645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => PROCESSING CACHE MISS RATES TO DETERMINE MEMORY SPACE TO ADD TO AN ACTIVE CACHE TO REDUCE A CACHE MISS RATE FOR THE ACTIVE CACHE [patent_app_type] => utility [patent_app_number] => 15/629249 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629249
Processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache Jun 20, 2017 Issued
Array ( [id] => 13738351 [patent_doc_number] => 20180373645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => PROCESSING CACHE MISS RATES TO DETERMINE MEMORY SPACE TO ADD TO AN ACTIVE CACHE TO REDUCE A CACHE MISS RATE FOR THE ACTIVE CACHE [patent_app_type] => utility [patent_app_number] => 15/629249 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629249
Processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache Jun 20, 2017 Issued
Array ( [id] => 12221879 [patent_doc_number] => 20180060239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/621401 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5895 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15621401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/621401
Disabling cache portions during low voltage operations Jun 12, 2017 Issued
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