Search

Daniel D. Tsui

Examiner (ID: 9882, Phone: (571)270-3253 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2132, 2182, 2185
Total Applications
717
Issued Applications
630
Pending Applications
46
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18677698 [patent_doc_number] => 20230315344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MAINTAINING QUALIY OF SERVICE OF NON-VOLATILE MEMORY DEVICES IN HETEROGENEOUS ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/706975 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706975
Maintaining quality of service of non-volatile memory devices in heterogeneous environment Mar 28, 2022 Issued
Array ( [id] => 18577349 [patent_doc_number] => 11733878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Data error correction for magnetic disks [patent_app_type] => utility [patent_app_number] => 17/707809 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8719 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707809
Data error correction for magnetic disks Mar 28, 2022 Issued
Array ( [id] => 18506257 [patent_doc_number] => 11704071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-18 [patent_title] => Delegating low priority tasks to a passive storage controller [patent_app_type] => utility [patent_app_number] => 17/706472 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706472
Delegating low priority tasks to a passive storage controller Mar 27, 2022 Issued
Array ( [id] => 18659693 [patent_doc_number] => 20230305700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SCALABLE QUALITY OF SERVICE (QoS) FOR A NONVOLATILE MEMORY EXPRESS(tm) ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/705076 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705076
Scalable quality of service (QoS) for a nonvolatile memory express(tm) environment Mar 24, 2022 Issued
Array ( [id] => 18826787 [patent_doc_number] => 11842063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Data placement and recovery in the event of partition failures [patent_app_type] => utility [patent_app_number] => 17/704978 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16560 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704978
Data placement and recovery in the event of partition failures Mar 24, 2022 Issued
Array ( [id] => 18749961 [patent_doc_number] => 11809272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Error correction code offload for a serially-attached memory device [patent_app_type] => utility [patent_app_number] => 17/696937 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6605 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696937
Error correction code offload for a serially-attached memory device Mar 16, 2022 Issued
Array ( [id] => 18651442 [patent_doc_number] => 20230297278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DATA STORAGE USING A SLIDING WINDOW CACHE IN A DATA GRID [patent_app_type] => utility [patent_app_number] => 17/697121 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697121
Data storage using a sliding window cache in a data grid Mar 16, 2022 Issued
Array ( [id] => 18795821 [patent_doc_number] => 11829608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Adaptive adjustment of resynchronization speed [patent_app_type] => utility [patent_app_number] => 17/695486 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695486
Adaptive adjustment of resynchronization speed Mar 14, 2022 Issued
Array ( [id] => 18591908 [patent_doc_number] => 11740804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => System and method for performing data striping [patent_app_type] => utility [patent_app_number] => 17/695012 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695012
System and method for performing data striping Mar 14, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18506256 [patent_doc_number] => 11704070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Managed NAND data compression [patent_app_type] => utility [patent_app_number] => 17/692732 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692732
Managed NAND data compression Mar 10, 2022 Issued
Array ( [id] => 18826791 [patent_doc_number] => 11842067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Memory controller, memory system including the same, and method of operating the memory system [patent_app_type] => utility [patent_app_number] => 17/690706 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 16610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690706
Memory controller, memory system including the same, and method of operating the memory system Mar 8, 2022 Issued
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