Search

Daniel D. Tsui

Examiner (ID: 14435)

Most Active Art Unit
2132
Art Unit(s)
2182, 2185, 2132
Total Applications
733
Issued Applications
639
Pending Applications
53
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18826787 [patent_doc_number] => 11842063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Data placement and recovery in the event of partition failures [patent_app_type] => utility [patent_app_number] => 17/704978 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16560 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704978
Data placement and recovery in the event of partition failures Mar 24, 2022 Issued
Array ( [id] => 18651442 [patent_doc_number] => 20230297278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DATA STORAGE USING A SLIDING WINDOW CACHE IN A DATA GRID [patent_app_type] => utility [patent_app_number] => 17/697121 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697121
Data storage using a sliding window cache in a data grid Mar 16, 2022 Issued
Array ( [id] => 18749961 [patent_doc_number] => 11809272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Error correction code offload for a serially-attached memory device [patent_app_type] => utility [patent_app_number] => 17/696937 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6605 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696937
Error correction code offload for a serially-attached memory device Mar 16, 2022 Issued
Array ( [id] => 18591908 [patent_doc_number] => 11740804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => System and method for performing data striping [patent_app_type] => utility [patent_app_number] => 17/695012 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695012
System and method for performing data striping Mar 14, 2022 Issued
Array ( [id] => 18795821 [patent_doc_number] => 11829608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Adaptive adjustment of resynchronization speed [patent_app_type] => utility [patent_app_number] => 17/695486 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695486
Adaptive adjustment of resynchronization speed Mar 14, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18022653 [patent_doc_number] => 20220374152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC) [patent_app_type] => utility [patent_app_number] => 17/694657 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694657
Low latency SSD read architecture with multi-level error correction codes (ECC) Mar 13, 2022 Issued
Array ( [id] => 18506256 [patent_doc_number] => 11704070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Managed NAND data compression [patent_app_type] => utility [patent_app_number] => 17/692732 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692732
Managed NAND data compression Mar 10, 2022 Issued
Array ( [id] => 18826791 [patent_doc_number] => 11842067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Memory controller, memory system including the same, and method of operating the memory system [patent_app_type] => utility [patent_app_number] => 17/690706 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 16610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690706
Memory controller, memory system including the same, and method of operating the memory system Mar 8, 2022 Issued
Array ( [id] => 18267367 [patent_doc_number] => 20230088609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MAGNETIC DISK APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 17/689242 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689242
Magnetic disk apparatus and method Mar 7, 2022 Issued
Array ( [id] => 18598931 [patent_doc_number] => 20230273730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => INCREASING RESILIENCY OF INPUT-OUTPUT OPERATIONS TO NETWORK INTERRUPTIONS [patent_app_type] => utility [patent_app_number] => 17/681999 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/681999
Increasing resiliency of input-output operations to network interruptions Feb 27, 2022 Issued
Array ( [id] => 18598938 [patent_doc_number] => 20230273737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => MEMORY BLOCK, MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/680388 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680388
Memory block, memory device for error correction operation and method thereof Feb 24, 2022 Issued
Array ( [id] => 18873370 [patent_doc_number] => 11861180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Error correction in memory system [patent_app_type] => utility [patent_app_number] => 17/680121 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 7844 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680121
Error correction in memory system Feb 23, 2022 Issued
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