Search

Daniel Elliot Namay

Examiner (ID: 8225, Phone: (571)270-5725 , Office: P/3749 )

Most Active Art Unit
3749
Art Unit(s)
3743, 3749, 3762, 4159
Total Applications
893
Issued Applications
621
Pending Applications
8
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18820783 [patent_doc_number] => 20230395124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => TIMING ADJUSTMENT FOR DATA INPUT/OUTPUT BUFFER CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/834754 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834754
Timing adjustment for data input/output buffer circuits Jun 6, 2022 Issued
Array ( [id] => 18061442 [patent_doc_number] => 20220392528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => METHOD FOR PROGRAMMING AN ARRAY OF RESISTIVE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/831948 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831948
Method for programming an array of resistive memory cells Jun 2, 2022 Issued
Array ( [id] => 17870422 [patent_doc_number] => 20220293159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/829579 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829579
Semiconductor device May 31, 2022 Issued
Array ( [id] => 19459956 [patent_doc_number] => 12100458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Systems and methods of correcting errors in unmatched memory devices [patent_app_type] => utility [patent_app_number] => 17/827562 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 21963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827562
Systems and methods of correcting errors in unmatched memory devices May 26, 2022 Issued
Array ( [id] => 19137860 [patent_doc_number] => 11972831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Receiver for receiving multi-level signal and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/827126 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 19706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827126
Receiver for receiving multi-level signal and memory device including the same May 26, 2022 Issued
Array ( [id] => 18812236 [patent_doc_number] => 20230386573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR [patent_app_type] => utility [patent_app_number] => 17/826180 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826180
First fire operation for ovonic threshold switch selector May 26, 2022 Issued
Array ( [id] => 17854924 [patent_doc_number] => 20220284967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DYNAMIC PROGRAM ERASE TARGETING WITH BIT ERROR RATE [patent_app_type] => utility [patent_app_number] => 17/826775 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826775
Dynamic program erase targeting with bit error rate May 26, 2022 Issued
Array ( [id] => 19328617 [patent_doc_number] => 12046306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Temperature dependent programming techniques in a memory device [patent_app_type] => utility [patent_app_number] => 17/826434 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826434
Temperature dependent programming techniques in a memory device May 26, 2022 Issued
Array ( [id] => 19123364 [patent_doc_number] => 11967358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Apparatuses and methods for bias temperature instability mitigation [patent_app_type] => utility [patent_app_number] => 17/825600 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825600
Apparatuses and methods for bias temperature instability mitigation May 25, 2022 Issued
Array ( [id] => 17854925 [patent_doc_number] => 20220284968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD AND APPARATUS TO MITIGATE HOT ELECTRON READ DISTURBS IN 3D NAND DEVICES [patent_app_type] => utility [patent_app_number] => 17/825960 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825960
Method and apparatus to mitigate hot electron read disturbs in 3D nand devices May 25, 2022 Issued
Array ( [id] => 18812241 [patent_doc_number] => 20230386578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/825439 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825439
Partial block handling protocol in a non-volatile memory device May 25, 2022 Issued
Array ( [id] => 19062909 [patent_doc_number] => 11942154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Non-volatile memory device and method of operating nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/825764 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 17689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825764
Non-volatile memory device and method of operating nonvolatile memory device May 25, 2022 Issued
Array ( [id] => 19168250 [patent_doc_number] => 11984161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Charge screening structure for spike current suppression in a memory array [patent_app_type] => utility [patent_app_number] => 17/824826 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 18126 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824826
Charge screening structure for spike current suppression in a memory array May 24, 2022 Issued
Array ( [id] => 19168254 [patent_doc_number] => 11984165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Memory device with reduced area [patent_app_type] => utility [patent_app_number] => 17/752662 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752662
Memory device with reduced area May 23, 2022 Issued
Array ( [id] => 19153569 [patent_doc_number] => 11978490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Back pattern counter measure for solid state drives [patent_app_type] => utility [patent_app_number] => 17/752112 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3873 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752112
Back pattern counter measure for solid state drives May 23, 2022 Issued
Array ( [id] => 18562740 [patent_doc_number] => 11727990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => 3D NAND flash and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/751432 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3088 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751432
3D NAND flash and operation method thereof May 22, 2022 Issued
Array ( [id] => 17853897 [patent_doc_number] => 20220283939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SLC CACHE ALLOCATION [patent_app_type] => utility [patent_app_number] => 17/750933 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750933
SLC cache allocation May 22, 2022 Issued
Array ( [id] => 17840470 [patent_doc_number] => 20220277776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => MEMORY COMPONENT FOR A SYSTEM-ON-CHIP DEVICE [patent_app_type] => utility [patent_app_number] => 17/745583 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745583
Memory component for a system-on-chip device May 15, 2022 Issued
Array ( [id] => 17811024 [patent_doc_number] => 20220262859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => CAPACITIVE PILLAR ARCHITECTURE FOR A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/735810 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735810
Capacitive pillar architecture for a memory array May 2, 2022 Issued
Array ( [id] => 18024028 [patent_doc_number] => 20220375527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => NON-VOLATILE MEMORY PROGRAMMING CIRCUIT AND A METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/733877 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733877
Non-volatile memory programming circuit and a method of programming non-volatile memory devices Apr 28, 2022 Issued
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