Search

Daniel Elliot Namay

Examiner (ID: 8225, Phone: (571)270-5725 , Office: P/3749 )

Most Active Art Unit
3749
Art Unit(s)
3743, 3749, 3762, 4159
Total Applications
893
Issued Applications
621
Pending Applications
8
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18408683 [patent_doc_number] => 20230170036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => ENVIRONMENTAL CONDITION TRACKING FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/456972 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456972
Environmental condition tracking for a memory system Nov 29, 2021 Issued
Array ( [id] => 18394552 [patent_doc_number] => 20230162773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Memory Device with Spin-Harvesting Structure [patent_app_type] => utility [patent_app_number] => 17/456088 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456088
Memory device with spin-harvesting structure Nov 21, 2021 Issued
Array ( [id] => 19639496 [patent_doc_number] => 12170109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Hybrid resistive memory [patent_app_type] => utility [patent_app_number] => 17/454311 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4111 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454311
Hybrid resistive memory Nov 9, 2021 Issued
Array ( [id] => 19123383 [patent_doc_number] => 11967377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Dynamically gated search lines for low-power multi-stage content addressable memory [patent_app_type] => utility [patent_app_number] => 17/522214 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522214
Dynamically gated search lines for low-power multi-stage content addressable memory Nov 8, 2021 Issued
Array ( [id] => 20495163 [patent_doc_number] => 12537039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/035013 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 61 [patent_no_of_words] => 35573 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035013
Semiconductor device Nov 8, 2021 Issued
Array ( [id] => 17917211 [patent_doc_number] => 20220319607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PROGRAMMING FOR THREE-DIMENSIONAL NAND MEMORY [patent_app_type] => utility [patent_app_number] => 17/518783 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518783
Programming for three-dimensional NAND memory Nov 3, 2021 Issued
Array ( [id] => 18207351 [patent_doc_number] => 20230053608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => HYBRID MEMORY SYSTEM CONFIGURABLE TO STORE NEURAL MEMORY WEIGHT DATA IN ANALOG FORM OR DIGITAL FORM [patent_app_type] => utility [patent_app_number] => 17/519241 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519241
Hybrid memory system configurable to store neural memory weight data in analog form or digital form Nov 3, 2021 Issued
Array ( [id] => 18781959 [patent_doc_number] => 11823724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Magneto-electric low power analogue magnetic tunnel junction memory [patent_app_type] => utility [patent_app_number] => 17/510436 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4092 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510436
Magneto-electric low power analogue magnetic tunnel junction memory Oct 25, 2021 Issued
Array ( [id] => 18798662 [patent_doc_number] => 11832530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Multi-bit memory cell, analog-to-digital converter, device and method [patent_app_type] => utility [patent_app_number] => 17/508819 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 11948 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508819
Multi-bit memory cell, analog-to-digital converter, device and method Oct 21, 2021 Issued
Array ( [id] => 17583377 [patent_doc_number] => 20220140232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PHASE-CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/507645 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/507645
Phase-change memory Oct 20, 2021 Issued
Array ( [id] => 17416814 [patent_doc_number] => 20220051718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => PHYSICALLY UNCLONABLE FUNCTION (PUF) GENERATION INVOLVING PROGRAMMING OF MARGINAL BITS [patent_app_type] => utility [patent_app_number] => 17/503890 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/503890
Physically unclonable function (PUF) generation involving programming of marginal bits Oct 17, 2021 Issued
Array ( [id] => 17389097 [patent_doc_number] => 20220036949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => PHYSICALLY UNCLONABLE FUNCTION (PUF) GENERATION INVOLVING HIGH SIDE PROGRAMMING OF BITS [patent_app_type] => utility [patent_app_number] => 17/503924 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/503924
Physically unclonable function (PUF) generation involving high side programming of bits Oct 17, 2021 Issued
Array ( [id] => 17840497 [patent_doc_number] => 20220277803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => FUSE FAULT REPAIR CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/498083 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498083
Fuse fault repair circuit Oct 10, 2021 Issued
Array ( [id] => 18768478 [patent_doc_number] => 11818902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Vertical 3D memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/497461 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497461
Vertical 3D memory device and method for manufacturing the same Oct 7, 2021 Issued
Array ( [id] => 17373409 [patent_doc_number] => 20220028461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/495645 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495645
Non-volatile memory device Oct 5, 2021 Issued
Array ( [id] => 18446890 [patent_doc_number] => 11682465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Reliable through-silicon vias [patent_app_type] => utility [patent_app_number] => 17/491164 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491164
Reliable through-silicon vias Sep 29, 2021 Issued
Array ( [id] => 19314217 [patent_doc_number] => 12040041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Control logic assemblies [patent_app_type] => utility [patent_app_number] => 17/448754 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 47 [patent_no_of_words] => 28049 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448754
Control logic assemblies Sep 23, 2021 Issued
Array ( [id] => 17346846 [patent_doc_number] => 20220013177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/485241 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485241
Memory device and erasing and verification method thereof Sep 23, 2021 Issued
Array ( [id] => 18271606 [patent_doc_number] => 20230092848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MULTI-DECK NON-VOLATILE MEMORY ARCHITECTURE WITH REDUCED TERMINATION TILE AREA [patent_app_type] => utility [patent_app_number] => 17/482578 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482578
Multi-deck non-volatile memory architecture with reduced termination tile area Sep 22, 2021 Issued
Array ( [id] => 18669710 [patent_doc_number] => 11776620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device including semiconductor element [patent_app_type] => utility [patent_app_number] => 17/478282 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 107 [patent_no_of_words] => 22367 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478282
Memory device including semiconductor element Sep 16, 2021 Issued
Menu