Search

Daniel Elliot Namay

Examiner (ID: 8225, Phone: (571)270-5725 , Office: P/3749 )

Most Active Art Unit
3749
Art Unit(s)
3743, 3749, 3762, 4159
Total Applications
893
Issued Applications
621
Pending Applications
8
Abandoned Applications
265

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20266820 [patent_doc_number] => 12437816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory, a memory system, and a method for operating memory [patent_app_type] => utility [patent_app_number] => 18/528454 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528454
Memory, a memory system, and a method for operating memory Dec 3, 2023 Issued
Array ( [id] => 20036050 [patent_doc_number] => 20250174272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => GENERATING AND USING A STATE TRANSITION MATRIX FOR DECODING DATA IN A DNA-BASED STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/523202 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523202
Generating and using a state transition matrix for decoding data in a DNA-based storage system Nov 28, 2023 Issued
Array ( [id] => 20305182 [patent_doc_number] => 12451178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Synapse device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/522109 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522109
Synapse device and method of operating the same Nov 27, 2023 Issued
Array ( [id] => 19879614 [patent_doc_number] => 20250111871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => MEMORY DEVICES HAVING A RANDOM NUMBER GENERATOR FOR PROTECTING MEMORY CELLS, AND METHODS FOR PROTECTING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/515690 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515690
Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices Nov 20, 2023 Issued
Array ( [id] => 19252467 [patent_doc_number] => 20240203464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DIRECTED TO WRITE-ONLY MODE REGISTER BITS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513317 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513317 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513317
Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same Nov 16, 2023 Issued
Array ( [id] => 20266807 [patent_doc_number] => 12437803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package [patent_app_type] => utility [patent_app_number] => 18/509315 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509315
Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package Nov 14, 2023 Issued
Array ( [id] => 19023231 [patent_doc_number] => 20240079402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => MEMORY DEVICE WITH A MULTIPLEXED COMMAND/ADDRESS BUS [patent_app_type] => utility [patent_app_number] => 18/389113 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389113
Memory device with a multiplexed command/address bus Nov 12, 2023 Issued
Array ( [id] => 20389085 [patent_doc_number] => 12488818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Circuit for aligning command input data and semiconducter device including the same [patent_app_type] => utility [patent_app_number] => 18/507296 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507296
Circuit for aligning command input data and semiconducter device including the same Nov 12, 2023 Issued
Array ( [id] => 20468309 [patent_doc_number] => 12524348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Operating method of set-associative cache and system including set-associative cache [patent_app_type] => utility [patent_app_number] => 18/505247 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505247
Operating method of set-associative cache and system including set-associative cache Nov 8, 2023 Issued
Array ( [id] => 19687737 [patent_doc_number] => 20250006282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/503386 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503386
Semiconductor device and method for manufacturing the same Nov 6, 2023 Issued
Array ( [id] => 20258808 [patent_doc_number] => 12431169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/503222 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 5583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503222
Semiconductor memory device Nov 6, 2023 Issued
Array ( [id] => 19007404 [patent_doc_number] => 20240071475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/493051 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493051
Memory device and operation method thereof Oct 23, 2023 Issued
Array ( [id] => 20258816 [patent_doc_number] => 12431178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Low-voltage sense amplifier for reading a state-programmable memory element [patent_app_type] => utility [patent_app_number] => 18/486206 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/486206
Low-voltage sense amplifier for reading a state-programmable memory element Oct 12, 2023 Issued
Array ( [id] => 20175711 [patent_doc_number] => 12394464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Hybrid FeRAM/OxRAM data storage circuit [patent_app_type] => utility [patent_app_number] => 18/379132 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 2114 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379132
Hybrid FeRAM/OxRAM data storage circuit Oct 10, 2023 Issued
Array ( [id] => 20175711 [patent_doc_number] => 12394464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Hybrid FeRAM/OxRAM data storage circuit [patent_app_type] => utility [patent_app_number] => 18/379132 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 2114 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379132
Hybrid FeRAM/OxRAM data storage circuit Oct 10, 2023 Issued
Array ( [id] => 20188510 [patent_doc_number] => 12399622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => High-level architecture for 3D-NAND based in-memory search [patent_app_type] => utility [patent_app_number] => 18/378960 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 9155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378960
High-level architecture for 3D-NAND based in-memory search Oct 10, 2023 Issued
Array ( [id] => 18958665 [patent_doc_number] => 20240046992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ELECTRICAL FUSE ONE TIME PROGRAMMABLE (OTP) MEMORY [patent_app_type] => utility [patent_app_number] => 18/482053 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482053
Electrical fuse one time programmable (OTP) memory Oct 5, 2023 Issued
Array ( [id] => 20274671 [patent_doc_number] => 12444455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory structure [patent_app_type] => utility [patent_app_number] => 18/376455 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2341 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376455
Memory structure Oct 3, 2023 Issued
Array ( [id] => 19749186 [patent_doc_number] => 20250037751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY DEVICES CONFIGURED WITH ADAPTIVE WORD LINE PULSE ADJUSTMENT AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/479300 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479300
Memory devices configured with adaptive word line pulse adjustment and methods for operating the same Oct 1, 2023 Issued
Array ( [id] => 19972216 [patent_doc_number] => 12340834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices [patent_app_type] => utility [patent_app_number] => 18/374151 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374151
Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices Sep 27, 2023 Issued
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