Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16903142 [patent_doc_number] => 20210182058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/169232 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169232
Instructions and logic to perform floating point and integer operations for machine learning Feb 4, 2021 Issued
Array ( [id] => 16957817 [patent_doc_number] => 11061678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 17/127213 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11178 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127213
Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit Dec 17, 2020 Issued
Array ( [id] => 16844723 [patent_doc_number] => 11016810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture [patent_app_type] => utility [patent_app_number] => 17/102643 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102643
Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture Nov 23, 2020 Issued
Array ( [id] => 17308995 [patent_doc_number] => 11210105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction [patent_app_type] => utility [patent_app_number] => 17/087556 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2740 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087556
Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction Nov 1, 2020 Issued
Array ( [id] => 16844679 [patent_doc_number] => 11016764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Vector processing unit [patent_app_type] => utility [patent_app_number] => 16/843015 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10716 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843015
Vector processing unit Apr 7, 2020 Issued
Array ( [id] => 16787968 [patent_doc_number] => 10990401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Computation engine with strided dot product [patent_app_type] => utility [patent_app_number] => 16/837631 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837631
Computation engine with strided dot product Mar 31, 2020 Issued
Array ( [id] => 17091590 [patent_doc_number] => 11119779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization [patent_app_type] => utility [patent_app_number] => 16/825383 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 18842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825383
Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization Mar 19, 2020 Issued
Array ( [id] => 16299746 [patent_doc_number] => 20200285469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => Cache Management Operations Using Streaming Engine [patent_app_type] => utility [patent_app_number] => 16/825348 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825348
Cache management operations using streaming engine Mar 19, 2020 Issued
Array ( [id] => 17046753 [patent_doc_number] => 11099933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Streaming engine with error detection, correction and restart [patent_app_type] => utility [patent_app_number] => 16/808683 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 25323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808683
Streaming engine with error detection, correction and restart Mar 3, 2020 Issued
Array ( [id] => 17076659 [patent_doc_number] => 11113057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Streaming engine with cache-like stream data storage and lifetime tracking [patent_app_type] => utility [patent_app_number] => 16/808653 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 25379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808653
Streaming engine with cache-like stream data storage and lifetime tracking Mar 3, 2020 Issued
Array ( [id] => 17288251 [patent_doc_number] => 11204801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Method and apparatus for scheduling thread order to improve cache efficiency [patent_app_type] => utility [patent_app_number] => 16/684077 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 23863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684077
Method and apparatus for scheduling thread order to improve cache efficiency Nov 13, 2019 Issued
Array ( [id] => 16810397 [patent_doc_number] => 20210132952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => CODE AND DATA SHARING AMONG MULTIPLE INDEPENDENT PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/675212 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675212
Code and data sharing among multiple independent processors Nov 4, 2019 Issued
Array ( [id] => 15902887 [patent_doc_number] => 20200150963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => PROCESSING DEVICE AND METHOD OF CONTROLLING PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 16/672569 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672569 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672569
Processing device and method of controlling processing device Nov 3, 2019 Issued
Array ( [id] => 17001253 [patent_doc_number] => 11080063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Processing device and method of controlling processing device [patent_app_type] => utility [patent_app_number] => 16/665449 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13433 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/665449
Processing device and method of controlling processing device Oct 27, 2019 Issued
Array ( [id] => 16794768 [patent_doc_number] => 20210124585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => CIRCUITRY AND METHODS [patent_app_type] => utility [patent_app_number] => 16/662396 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662396
Circuitry and methods Oct 23, 2019 Issued
Array ( [id] => 15997847 [patent_doc_number] => 20200174794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => ILLEGAL INSTRUCTION EXCEPTION HANDLING [patent_app_type] => utility [patent_app_number] => 16/661223 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661223
Illegal instruction exception handling Oct 22, 2019 Issued
Array ( [id] => 16077353 [patent_doc_number] => 20200192663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => APPARATUS AND METHOD FOR COMPLEX MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 16/657007 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657007
Apparatus and method for complex multiplication Oct 17, 2019 Issued
Array ( [id] => 15500529 [patent_doc_number] => 20200050453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => APPARATUS AND METHODS FOR MATRIX MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 16/655688 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655688
Apparatus and methods for matrix multiplication Oct 16, 2019 Issued
Array ( [id] => 15439927 [patent_doc_number] => 20200034147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => PREDICTING A TABLE OF CONTENTS POINTER VALUE RESPONSIVE TO BRANCHING TO A SUBROUTINE [patent_app_type] => utility [patent_app_number] => 16/590439 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590439
Predicting a table of contents pointer value responsive to branching to a subroutine Oct 1, 2019 Issued
Array ( [id] => 17308984 [patent_doc_number] => 11210094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling [patent_app_type] => utility [patent_app_number] => 16/585427 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 26077 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585427
Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling Sep 26, 2019 Issued
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