
Daniel H. Pan
Examiner (ID: 18277)
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2302, 2182, 2183, 2783, 2315, 2899 |
| Total Applications | 1471 |
| Issued Applications | 1279 |
| Pending Applications | 50 |
| Abandoned Applications | 145 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11731450
[patent_doc_number] => 20170192893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'INSTRUCTION TO CANCEL OUTSTANDING CACHE PREFETCHES'
[patent_app_type] => utility
[patent_app_number] => 15/387956
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 19836
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387956
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/387956 | Instruction to cancel outstanding cache prefetches | Dec 21, 2016 | Issued |
Array
(
[id] => 14009325
[patent_doc_number] => 10223121
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => Method and apparatus for supporting quasi-posted loads
[patent_app_type] => utility
[patent_app_number] => 15/388744
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 22412
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388744
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/388744 | Method and apparatus for supporting quasi-posted loads | Dec 21, 2016 | Issued |
Array
(
[id] => 13130209
[patent_doc_number] => 10083035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization
[patent_app_type] => utility
[patent_app_number] => 15/384580
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 34
[patent_no_of_words] => 18594
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 709
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384580
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384580 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Dec 19, 2016 | Issued |
Array
(
[id] => 13120395
[patent_doc_number] => 10078551
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-18
[patent_title] => Streaming engine with error detection, correction and restart
[patent_app_type] => utility
[patent_app_number] => 15/384355
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 45
[patent_no_of_words] => 25005
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 488
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384355
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384355 | Streaming engine with error detection, correction and restart | Dec 19, 2016 | Issued |
Array
(
[id] => 13083217
[patent_doc_number] => 10061675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-28
[patent_title] => Streaming engine with deferred exception reporting
[patent_app_type] => utility
[patent_app_number] => 15/384378
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 45
[patent_no_of_words] => 25112
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384378
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384378 | Streaming engine with deferred exception reporting | Dec 19, 2016 | Issued |
Array
(
[id] => 12845077
[patent_doc_number] => 20180173532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTABLE AT EACH DIMENSION
[patent_app_type] => utility
[patent_app_number] => 15/384451
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21000
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384451
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384451 | Streaming engine with multi dimensional circular addressing selectable at each dimension | Dec 19, 2016 | Issued |
Array
(
[id] => 14523591
[patent_doc_number] => 10339057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-02
[patent_title] => Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets
[patent_app_type] => utility
[patent_app_number] => 15/384487
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 39
[patent_no_of_words] => 21043
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 452
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384487
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384487 | Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets | Dec 19, 2016 | Issued |
Array
(
[id] => 11629522
[patent_doc_number] => 20170139710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-18
[patent_title] => 'STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKING'
[patent_app_type] => utility
[patent_app_number] => 15/384342
[patent_app_country] => US
[patent_app_date] => 2016-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 25637
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384342
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384342 | Streaming engine with cache-like stream data storage and lifetime tracking | Dec 19, 2016 | Issued |
Array
(
[id] => 11445243
[patent_doc_number] => 20170046264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'TECHNIQUES FOR IMPLEMENTING BARRIERS TO EFFICIENTLY SUPPORT CUMULATIVITY IN A WEAKLY-ORDERED MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/339191
[patent_app_country] => US
[patent_app_date] => 2016-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10581
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339191
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/339191 | Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system | Oct 30, 2016 | Issued |
Array
(
[id] => 11445285
[patent_doc_number] => 20170046306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'DATA PROCESSING METHOD, PROCESSOR, AND DATA PROCESSING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/337872
[patent_app_country] => US
[patent_app_date] => 2016-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8429
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337872
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/337872 | Data processing method, processor, and data processing device | Oct 27, 2016 | Issued |
Array
(
[id] => 11917249
[patent_doc_number] => 09785435
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-10
[patent_title] => 'Floating point instruction with selectable comparison attributes'
[patent_app_type] => utility
[patent_app_number] => 15/335914
[patent_app_country] => US
[patent_app_date] => 2016-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 33
[patent_no_of_words] => 11527
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335914
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/335914 | Floating point instruction with selectable comparison attributes | Oct 26, 2016 | Issued |
Array
(
[id] => 13974319
[patent_doc_number] => 10216516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Fused adjacent memory stores
[patent_app_type] => utility
[patent_app_number] => 15/281957
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 15315
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281957
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281957 | Fused adjacent memory stores | Sep 29, 2016 | Issued |
Array
(
[id] => 13919669
[patent_doc_number] => 10203957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-12
[patent_title] => Processor with improved alias queue and store collision detection to reduce memory violations and load replays
[patent_app_type] => utility
[patent_app_number] => 15/281644
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9565
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281644
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281644 | Processor with improved alias queue and store collision detection to reduce memory violations and load replays | Sep 29, 2016 | Issued |
Array
(
[id] => 11875335
[patent_doc_number] => 09747106
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-29
[patent_title] => 'Allocating multiple operand data areas of a computer instruction within a program buffer'
[patent_app_type] => utility
[patent_app_number] => 15/282129
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6025
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282129
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282129 | Allocating multiple operand data areas of a computer instruction within a program buffer | Sep 29, 2016 | Issued |
Array
(
[id] => 14034411
[patent_doc_number] => 10228956
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-12
[patent_title] => Supporting binary translation alias detection in an out-of-order processor
[patent_app_type] => utility
[patent_app_number] => 15/282266
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 16637
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282266
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282266 | Supporting binary translation alias detection in an out-of-order processor | Sep 29, 2016 | Issued |
Array
(
[id] => 13973787
[patent_doc_number] => 10216246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Multi-level loops for computer processor control
[patent_app_type] => utility
[patent_app_number] => 15/281651
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16777
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281651
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281651 | Multi-level loops for computer processor control | Sep 29, 2016 | Issued |
Array
(
[id] => 12611790
[patent_doc_number] => 20180095760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING
[patent_app_type] => utility
[patent_app_number] => 15/281380
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281380
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281380 | INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING | Sep 29, 2016 | Abandoned |
Array
(
[id] => 12611766
[patent_doc_number] => 20180095752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => INSTRUCTION PREDECODING
[patent_app_type] => utility
[patent_app_number] => 15/281226
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281226
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281226 | Instruction predecoding | Sep 29, 2016 | Issued |
Array
(
[id] => 12611775
[patent_doc_number] => 20180095755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => DECIMAL LOAD IMMEDIATE INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 15/281181
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281181
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281181 | Decimal load immediate instruction | Sep 29, 2016 | Issued |
Array
(
[id] => 12611787
[patent_doc_number] => 20180095759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => SUSPENDABLE LOAD ADDRESS TRACKING INSIDE TRANSACTIONS
[patent_app_type] => utility
[patent_app_number] => 15/282011
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14131
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282011
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282011 | Suspendable load address tracking inside transactions | Sep 29, 2016 | Issued |