Search

Daniel H. Pan

Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2315, 2182, 2783, 2899, 2302, 2183
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11396989 [patent_doc_number] => 20170017525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'HONORING HARDWARE ENTITLEMENT OF A HARDWARE THREAD' [patent_app_type] => utility [patent_app_number] => 15/279682 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279682
Honoring hardware entitlement of a hardware thread Sep 28, 2016 Issued
Array ( [id] => 12187527 [patent_doc_number] => 20180046463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SYSTEM AND METHOD FOR LOAD AND STORE QUEUE ALLOCATIONS AT ADDRESS GENERATION TIME' [patent_app_type] => utility [patent_app_number] => 15/236882 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236882
System and method for load and store queue allocations at address generation time Aug 14, 2016 Issued
Array ( [id] => 12173785 [patent_doc_number] => 09891928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Propagation of updates to per-core-instantiated architecturally-visible storage resource' [patent_app_type] => utility [patent_app_number] => 15/232506 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 39290 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232506
Propagation of updates to per-core-instantiated architecturally-visible storage resource Aug 8, 2016 Issued
Array ( [id] => 13029175 [patent_doc_number] => 10037207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Power management of branch predictors in a computer processor [patent_app_type] => utility [patent_app_number] => 15/220986 [patent_app_country] => US [patent_app_date] => 2016-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6386 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220986 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220986
Power management of branch predictors in a computer processor Jul 26, 2016 Issued
Array ( [id] => 12986050 [patent_doc_number] => 20170344377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => POWER MANAGEMENT OF BRANCH PREDICTORS IN A COMPUTER PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/165439 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165439
Power management of branch predictors in a computer processor May 25, 2016 Issued
Array ( [id] => 17325289 [patent_doc_number] => 11216301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Process scheduling in a processing system having at least one processor and shared hardware resources [patent_app_type] => utility [patent_app_number] => 16/090079 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9061 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16090079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/090079
Process scheduling in a processing system having at least one processor and shared hardware resources Apr 11, 2016 Issued
Array ( [id] => 16698654 [patent_doc_number] => 10949251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => System and method to accelerate reduce operations in graphics processor [patent_app_type] => utility [patent_app_number] => 16/066652 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 16282 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16066652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/066652
System and method to accelerate reduce operations in graphics processor Mar 31, 2016 Issued
Array ( [id] => 11708922 [patent_doc_number] => 20170177422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'TRANSLATION ENTRY INVALIDATION IN A MULTITHREADED DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/082830 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082830
Translation entry invalidation in a multithreaded data processing system Mar 27, 2016 Issued
Array ( [id] => 11606494 [patent_doc_number] => 20170123797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'HARDWARE-BASED RUN-TIME MITIGATION OF CONDITIONAL BRANCHES' [patent_app_type] => utility [patent_app_number] => 15/077936 [patent_app_country] => US [patent_app_date] => 2016-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10652 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15077936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/077936
Hardware-based run-time mitigation of conditional branches Mar 22, 2016 Issued
Array ( [id] => 13029183 [patent_doc_number] => 10037211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Operation of a multi-slice processor with an expanded merge fetching queue [patent_app_type] => utility [patent_app_number] => 15/077015 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15077015 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/077015
Operation of a multi-slice processor with an expanded merge fetching queue Mar 21, 2016 Issued
Array ( [id] => 13041009 [patent_doc_number] => 10042640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Processing queue management [patent_app_type] => utility [patent_app_number] => 15/076889 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3301 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15076889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/076889
Processing queue management Mar 21, 2016 Issued
Array ( [id] => 11951315 [patent_doc_number] => 20170255467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'Apparatus for Information Processing with Loop Cache and Associated Methods' [patent_app_type] => utility [patent_app_number] => 15/061018 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061018
Apparatus for information processing with loop cache and associated methods Mar 3, 2016 Issued
Array ( [id] => 11951314 [patent_doc_number] => 20170255465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR PREVENTING EARLY DEPENDENT INSTRUCTION WAKEUP' [patent_app_type] => utility [patent_app_number] => 15/060690 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060690
Operation of a multi-slice processor preventing early dependent instruction wakeup Mar 3, 2016 Issued
Array ( [id] => 11951312 [patent_doc_number] => 20170255463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DYNAMIC SWITCHING OF INSTRUCTION ISSUANCE ORDER' [patent_app_type] => utility [patent_app_number] => 15/059853 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059853
Operation of a multi-slice processor implementing dynamic switching of instruction issuance order Mar 2, 2016 Issued
Array ( [id] => 13083035 [patent_doc_number] => 10061584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Store nullification in the target field [patent_app_type] => utility [patent_app_number] => 15/060404 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15862 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060404
Store nullification in the target field Mar 2, 2016 Issued
Array ( [id] => 11516266 [patent_doc_number] => 20170083340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'INSTRUCTION BLOCK ADDRESS REGISTER' [patent_app_type] => utility [patent_app_number] => 15/060483 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060483
Instruction block address register Mar 2, 2016 Issued
Array ( [id] => 13891431 [patent_doc_number] => 10198263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Write nullification [patent_app_type] => utility [patent_app_number] => 15/060413 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 16148 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060413
Write nullification Mar 2, 2016 Issued
Array ( [id] => 13017283 [patent_doc_number] => 10031756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Multi-nullification [patent_app_type] => utility [patent_app_number] => 15/060445 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17285 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060445
Multi-nullification Mar 2, 2016 Issued
Array ( [id] => 11838631 [patent_doc_number] => 20170220352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'ACCESSING DATA IN MULTI-DIMENSIONAL TENSORS' [patent_app_type] => utility [patent_app_number] => 15/014265 [patent_app_country] => US [patent_app_date] => 2016-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9291 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15014265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/014265
Accessing data in multi-dimensional tensors Feb 2, 2016 Issued
Array ( [id] => 11465644 [patent_doc_number] => 09582274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-28 [patent_title] => 'Architected store and verify guard word instructions' [patent_app_type] => utility [patent_app_number] => 14/989240 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 11977 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989240
Architected store and verify guard word instructions Jan 5, 2016 Issued
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