Search

Daniel H. Pan

Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2315, 2182, 2783, 2899, 2302, 2183
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11359043 [patent_doc_number] => 09535696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-03 [patent_title] => 'Instruction to cancel outstanding cache prefetches' [patent_app_type] => utility [patent_app_number] => 14/987411 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 19822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14987411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/987411
Instruction to cancel outstanding cache prefetches Jan 3, 2016 Issued
Array ( [id] => 11716915 [patent_doc_number] => 20170185414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'SCATTER REDUCTION INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 15/301206 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15301206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/301206
Scatter reduction instruction Dec 23, 2015 Issued
Array ( [id] => 13817587 [patent_doc_number] => 10185562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Conflict mask generation [patent_app_type] => utility [patent_app_number] => 15/301224 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15301224 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/301224
Conflict mask generation Dec 23, 2015 Issued
Array ( [id] => 11452170 [patent_doc_number] => 09575815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-21 [patent_title] => 'Translation entry invalidation in a multithreaded data processing system' [patent_app_type] => utility [patent_app_number] => 14/977797 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11758 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977797
Translation entry invalidation in a multithreaded data processing system Dec 21, 2015 Issued
Array ( [id] => 11245272 [patent_doc_number] => 09471314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Auxiliary perceptron branch predictor with magnitude usage limit' [patent_app_type] => utility [patent_app_number] => 14/969535 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969535
Auxiliary perceptron branch predictor with magnitude usage limit Dec 14, 2015 Issued
Array ( [id] => 11509034 [patent_doc_number] => 09600194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Integrating sign extensions for loads' [patent_app_type] => utility [patent_app_number] => 14/952078 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952078
Integrating sign extensions for loads Nov 24, 2015 Issued
Array ( [id] => 15757691 [patent_doc_number] => 10620957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Method for forming constant extensions in the same execute packet in a VLIW processor [patent_app_type] => utility [patent_app_number] => 14/920402 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 12346 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920402
Method for forming constant extensions in the same execute packet in a VLIW processor Oct 21, 2015 Issued
Array ( [id] => 11531145 [patent_doc_number] => 20170091124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'EXCEPTION PRESERVING PARALLEL DATA PROCESSING OF STRING AND UNSTRUCTURED TEXT' [patent_app_type] => utility [patent_app_number] => 14/869181 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6448 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869181 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869181
Exception preserving parallel data processing of string and unstructured text Sep 28, 2015 Issued
Array ( [id] => 10746125 [patent_doc_number] => 20160092276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INDEPENDENT MAPPING OF THREADS' [patent_app_type] => utility [patent_app_number] => 14/869305 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4819 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869305
Independent mapping of threads Sep 28, 2015 Issued
Array ( [id] => 14766665 [patent_doc_number] => 10394729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Speculative and iterative execution of delayed data flow graphs [patent_app_type] => utility [patent_app_number] => 15/509836 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 12304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15509836 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/509836
Speculative and iterative execution of delayed data flow graphs Sep 21, 2015 Issued
Array ( [id] => 13679841 [patent_doc_number] => 20160378657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => NON-DEFAULT INSTRUCTION HANDLING WITHIN TRANSACTION [patent_app_type] => utility [patent_app_number] => 14/845382 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845382 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845382
Non-default instruction handling within transaction Sep 3, 2015 Issued
Array ( [id] => 12194568 [patent_doc_number] => 09898299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Dynamic thread sharing in branch prediction structures' [patent_app_type] => utility [patent_app_number] => 14/820090 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7010 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/820090
Dynamic thread sharing in branch prediction structures Aug 5, 2015 Issued
Array ( [id] => 15167323 [patent_doc_number] => 10489155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Mixed-width SIMD operations using even/odd register pairs for wide data elements [patent_app_type] => utility [patent_app_number] => 14/805456 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7779 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14805456 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/805456
Mixed-width SIMD operations using even/odd register pairs for wide data elements Jul 20, 2015 Issued
Array ( [id] => 15058855 [patent_doc_number] => 10459731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Sliding window operation [patent_app_type] => utility [patent_app_number] => 14/803728 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7858 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/803728
Sliding window operation Jul 19, 2015 Issued
Array ( [id] => 13679473 [patent_doc_number] => 20160378473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTION AND LOGIC FOR CHARACTERIZATION OF DATA ACCESS [patent_app_type] => utility [patent_app_number] => 14/752014 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752014
Instruction and logic for characterization of data access Jun 25, 2015 Issued
Array ( [id] => 13679493 [patent_doc_number] => 20160378483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => REUSE OF DECODED INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 14/752596 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752596
Reuse of decoded instructions Jun 25, 2015 Issued
Array ( [id] => 12114346 [patent_doc_number] => 09870339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Hardware processors and methods for tightly-coupled heterogeneous computing' [patent_app_type] => utility [patent_app_number] => 14/752047 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 19255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752047
Hardware processors and methods for tightly-coupled heterogeneous computing Jun 25, 2015 Issued
Array ( [id] => 12100979 [patent_doc_number] => 09858074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Non-default instruction handling within transaction' [patent_app_type] => utility [patent_app_number] => 14/751950 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17961 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751950 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751950
Non-default instruction handling within transaction Jun 25, 2015 Issued
Array ( [id] => 11027553 [patent_doc_number] => 20160224509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH ASYMMETRIC MULTI-THREADING' [patent_app_type] => utility [patent_app_number] => 14/716216 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21761 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716216
Vector processor configured to operate on variable length vectors with asymmetric multi-threading May 18, 2015 Issued
Array ( [id] => 10342360 [patent_doc_number] => 20150227365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Processor Supporting Arithmetic Instructions with Branch on Overflow & Methods' [patent_app_type] => utility [patent_app_number] => 14/612104 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612104 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612104
Processor supporting arithmetic instructions with branch on overflow and methods Feb 1, 2015 Issued
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