Daniel H. Pan

Array ( [id] => 12114346 [patent_doc_number] => 09870339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Hardware processors and methods for tightly-coupled heterogeneous computing' [patent_app_type] => utility [patent_app_number] => 14/752047 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 19255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027553 [patent_doc_number] => 20160224509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH ASYMMETRIC MULTI-THREADING' [patent_app_type] => utility [patent_app_number] => 14/716216 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21761 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10342360 [patent_doc_number] => 20150227365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Processor Supporting Arithmetic Instructions with Branch on Overflow & Methods' [patent_app_type] => utility [patent_app_number] => 14/612104 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173775 [patent_doc_number] => 09891918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Fractional use of prediction history storage for operating system routines' [patent_app_type] => utility [patent_app_number] => 14/605943 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10320607 [patent_doc_number] => 20150205611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Stack Pointer Value Prediction' [patent_app_type] => utility [patent_app_number] => 14/596407 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982589 [patent_doc_number] => 20160179533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 14/581285 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13988 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982601 [patent_doc_number] => 20160179545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING' [patent_app_type] => utility [patent_app_number] => 14/581268 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982583 [patent_doc_number] => 20160179527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTER STATE OF A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/581535 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982594 [patent_doc_number] => 20160179537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A SET OF VECTOR ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/581478 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 18297 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982582 [patent_doc_number] => 20160179526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE' [patent_app_type] => utility [patent_app_number] => 14/581289 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12571035 [patent_doc_number] => 10019263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Reordered speculative instruction sequences with a disambiguation-free out of order load store queue [patent_app_type] => utility [patent_app_number] => 14/569551 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13426 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13055147 [patent_doc_number] => 10048964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Disambiguation-free out of order load store queue [patent_app_type] => utility [patent_app_number] => 14/569543 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13406 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10210638 [patent_doc_number] => 20150095629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD AND SYSTEM FOR IMPLEMENTING RECOVERY FROM SPECULATIVE FORWARDING MISS-PREDICTIONS/ERRORS RESULTING FROM LOAD STORE REORDERING AND OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/567699 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13926 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12474840 [patent_doc_number] => 09990198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Instruction definition to implement load store reordering and optimization [patent_app_type] => utility [patent_app_number] => 14/567731 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13450 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10210627 [patent_doc_number] => 20150095618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A UNIFIED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/567797 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10249938 [patent_doc_number] => 20150134934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A DISTRIBUTED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/559740 [patent_app_country] => US [patent_app_date] => 2014-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14559740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746080 [patent_doc_number] => 20160092231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'INDEPENDENT MAPPING OF THREADS' [patent_app_type] => utility [patent_app_number] => 14/501152 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4819 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746090 [patent_doc_number] => 20160092241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SINGLE INSTRUCTION ARRAY INDEX COMPUTATION' [patent_app_type] => utility [patent_app_number] => 14/500171 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14500171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746084 [patent_doc_number] => 20160092235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVED THREAD SELECTION' [patent_app_type] => utility [patent_app_number] => 14/497974 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10746069 [patent_doc_number] => 20160092221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'DEPENDENCY-PREDICTION OF INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/498938 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11486 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498938 [rel_patent_id] =>[rel_patent_doc_number] =>)