Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13083359 [patent_doc_number] => 10061746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Instruction and logic for a vector format for processing computations [patent_app_type] => utility [patent_app_number] => 14/498064 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 32 [patent_no_of_words] => 21720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498064
Instruction and logic for a vector format for processing computations Sep 25, 2014 Issued
Array ( [id] => 12454059 [patent_doc_number] => 09983884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Method and apparatus for SIMD structured branching [patent_app_type] => utility [patent_app_number] => 14/498561 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11066 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498561
Method and apparatus for SIMD structured branching Sep 25, 2014 Issued
Array ( [id] => 11680227 [patent_doc_number] => 09678758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Coprocessor for out-of-order loads' [patent_app_type] => utility [patent_app_number] => 14/499044 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8118 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499044 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499044
Coprocessor for out-of-order loads Sep 25, 2014 Issued
Array ( [id] => 10748091 [patent_doc_number] => 20160094241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'APPARATUS AND METHOD FOR VECTOR COMPRESSION' [patent_app_type] => utility [patent_app_number] => 14/499038 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16551 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499038 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499038
Apparatus and method for vector compression Sep 25, 2014 Issued
Array ( [id] => 10746083 [patent_doc_number] => 20160092234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'METHOD AND APPARATUS FOR SPECULATIVE VECTORIZATION' [patent_app_type] => utility [patent_app_number] => 14/497833 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15482 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/497833
Method and apparatus for speculative vectorization Sep 25, 2014 Issued
Array ( [id] => 10462132 [patent_doc_number] => 20150347147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'ABSOLUTE ADDRESS BRANCHING IN A FIXED-WIDTH REDUCED INSTRUCTION SET COMPUTING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/478093 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/478093
Absolute address branching in a fixed-width reduced instruction set computing architecture Sep 4, 2014 Issued
Array ( [id] => 10462133 [patent_doc_number] => 20150347148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'RELATIVE OFFSET BRANCHING IN A FIXED-WIDTH REDUCED INSTRUCTION SET COMPUTING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/478114 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9036 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478114 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/478114
Relative offset branching in a fixed-width reduced instruction set computing architecture Sep 4, 2014 Issued
Array ( [id] => 11416731 [patent_doc_number] => 09563558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system' [patent_app_type] => utility [patent_app_number] => 14/472056 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10582 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14472056 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/472056
Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system Aug 27, 2014 Issued
Array ( [id] => 12352101 [patent_doc_number] => 09952876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Optimize control-flow convergence on SIMD engine using divergence depth [patent_app_type] => utility [patent_app_number] => 14/468904 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5861 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468904 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/468904
Optimize control-flow convergence on SIMD engine using divergence depth Aug 25, 2014 Issued
Array ( [id] => 10215771 [patent_doc_number] => 20150100763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'DECODING A COMPLEX PROGRAM INSTRUCTION CORRESPONDING TO MULTIPLE MICRO-OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/466183 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466183 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466183
Decoding a complex program instruction corresponding to multiple micro-operations Aug 21, 2014 Issued
Array ( [id] => 10215763 [patent_doc_number] => 20150100755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD FOR CONTROLLING PERFORMANCE OF SPECULATIVE VECTOR OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/461664 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12362 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14461664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/461664
Data processing apparatus and method for controlling performance of speculative vector operations Aug 17, 2014 Issued
Array ( [id] => 9866670 [patent_doc_number] => 20150046689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 14/447682 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8114 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447682 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/447682
ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT Jul 30, 2014 Abandoned
Array ( [id] => 11636879 [patent_doc_number] => 09658853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Techniques for increasing instruction issue rate and reducing latency in an out-of order processor' [patent_app_type] => utility [patent_app_number] => 14/448790 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8292 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14448790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/448790
Techniques for increasing instruction issue rate and reducing latency in an out-of order processor Jul 30, 2014 Issued
Array ( [id] => 11523406 [patent_doc_number] => 09606803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Highly integrated scalable, flexible DSP megamodule architecture' [patent_app_type] => utility [patent_app_number] => 14/331986 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 17057 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331986 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331986
Highly integrated scalable, flexible DSP megamodule architecture Jul 14, 2014 Issued
Array ( [id] => 10284330 [patent_doc_number] => 20150169328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'FRAMEWORK TO PROVIDE TIME BOUND EXECUTION OF CO-PROCESSOR COMMANDS' [patent_app_type] => utility [patent_app_number] => 14/310283 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6530 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/310283
Framework to provide time bound execution of co-processor commands Jun 19, 2014 Issued
Array ( [id] => 11465692 [patent_doc_number] => 09582323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Honoring hardware entitlement of a hardware thread' [patent_app_type] => utility [patent_app_number] => 14/309136 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14309136 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/309136
Honoring hardware entitlement of a hardware thread Jun 18, 2014 Issued
Array ( [id] => 10439195 [patent_doc_number] => 20150324207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PROCESSING OF MULTIPLE INSTRUCTION STREAMS IN A PARALLEL SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/302589 [patent_app_country] => US [patent_app_date] => 2014-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5296 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14302589 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/302589
Processing of multiple instruction streams in a parallel slice processor Jun 11, 2014 Issued
Array ( [id] => 10439194 [patent_doc_number] => 20150324206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING' [patent_app_type] => utility [patent_app_number] => 14/300563 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/300563
Parallel slice processor with dynamic instruction stream mapping Jun 9, 2014 Issued
Array ( [id] => 10439194 [patent_doc_number] => 20150324206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING' [patent_app_type] => utility [patent_app_number] => 14/300563 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/300563
Parallel slice processor with dynamic instruction stream mapping Jun 9, 2014 Issued
Array ( [id] => 10462131 [patent_doc_number] => 20150347146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'RELATIVE OFFSET BRANCHING IN A FIXED-WIDTH REDUCED INSTRUCTION SET COMPUTING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/291693 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14291693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/291693
Relative offset branching in a fixed-width reduced instruction set computing architecture May 29, 2014 Issued
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