Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11306522 [patent_doc_number] => 09513920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Computer processor employing split-stream encoding' [patent_app_type] => utility [patent_app_number] => 14/290108 [patent_app_country] => US [patent_app_date] => 2014-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9416 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14290108 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/290108
Computer processor employing split-stream encoding May 28, 2014 Issued
Array ( [id] => 10454109 [patent_doc_number] => 20150339124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'SYSTEM AND METHOD FOR SELECTIVELY ALLOCATING ENTRIES AT A BRANCH TARGET BUFFER' [patent_app_type] => utility [patent_app_number] => 14/282290 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14282290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/282290
System and method for selectively allocating entries at a branch target buffer May 19, 2014 Issued
Array ( [id] => 10454205 [patent_doc_number] => 20150339220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METHODS AND APPARATUS TO USE AN ACCESS TRIGGERED COMPUTER ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/282912 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14282912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/282912
Methods and apparatus to use an access triggered computer architecture May 19, 2014 Issued
Array ( [id] => 9912104 [patent_doc_number] => 20150067307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'PROPAGATION OF UPDATES TO PER-CORE-INSTANTIATED ARCHITECTURALLY-VISIBLE STORAGE RESOURCE' [patent_app_type] => utility [patent_app_number] => 14/281796 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 39239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281796
Propagation of updates to per-core-instantiated architecturally-visible storage resource May 18, 2014 Issued
Array ( [id] => 12173784 [patent_doc_number] => 09891927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Inter-core communication via uncore RAM' [patent_app_type] => utility [patent_app_number] => 14/281551 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 39105 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281551
Inter-core communication via uncore RAM May 18, 2014 Issued
Array ( [id] => 11924530 [patent_doc_number] => 09792112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Propagation of microcode patches to multiple cores in multicore microprocessor' [patent_app_type] => utility [patent_app_number] => 14/281786 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 39254 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281786 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281786
Propagation of microcode patches to multiple cores in multicore microprocessor May 18, 2014 Issued
Array ( [id] => 9800783 [patent_doc_number] => 20150012727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/279962 [patent_app_country] => US [patent_app_date] => 2014-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8635 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279962 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279962
PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE May 15, 2014 Abandoned
Array ( [id] => 10439192 [patent_doc_number] => 20150324204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING' [patent_app_type] => utility [patent_app_number] => 14/274927 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4464 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274927
Parallel slice processor with dynamic instruction stream mapping May 11, 2014 Issued
Array ( [id] => 10439193 [patent_doc_number] => 20150324205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PROCESSING OF MULTIPLE INSTRUCTION STREAMS IN A PARALLEL SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/274942 [patent_app_country] => US [patent_app_date] => 2014-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5278 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274942
Processing of multiple instruction streams in a parallel slice processor May 11, 2014 Issued
Array ( [id] => 11306648 [patent_doc_number] => 09514045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system' [patent_app_type] => utility [patent_app_number] => 14/245156 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10525 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245156
Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system Apr 3, 2014 Issued
Array ( [id] => 11754583 [patent_doc_number] => 09712614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Communication system and its method and communication apparatus and its method' [patent_app_type] => utility [patent_app_number] => 14/229153 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 19260 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229153
Communication system and its method and communication apparatus and its method Mar 27, 2014 Issued
Array ( [id] => 10242932 [patent_doc_number] => 20150127927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'EFFICIENT HARDWARE DISPATCHING OF CONCURRENT FUNCTIONS IN MULTICORE PROCESSORS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/224619 [patent_app_country] => US [patent_app_date] => 2014-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14224619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/224619
EFFICIENT HARDWARE DISPATCHING OF CONCURRENT FUNCTIONS IN MULTICORE PROCESSORS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA Mar 24, 2014 Abandoned
Array ( [id] => 10384112 [patent_doc_number] => 20150269119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Merging and Sorting Arrays on an SIMD Processor' [patent_app_type] => utility [patent_app_number] => 14/219391 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219391
Merging and sorting arrays on an SIMD processor Mar 18, 2014 Issued
Array ( [id] => 10922172 [patent_doc_number] => 20140325192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MEMRISTOR BASED MULTITHREADING' [patent_app_type] => utility [patent_app_number] => 14/219030 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6360 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219030 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219030
Memristor based multithreading Mar 18, 2014 Issued
Array ( [id] => 10383950 [patent_doc_number] => 20150268957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'DYNAMIC THREAD SHARING IN BRANCH PREDICTION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/219565 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219565
Dynamic thread sharing in branch prediction structures Mar 18, 2014 Issued
Array ( [id] => 9745719 [patent_doc_number] => 20140281438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR A DELAYED BRANCH IMPLEMENTATION BY USING A FRONT END TRACK TABLE' [patent_app_type] => utility [patent_app_number] => 14/216683 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216683
Method for a delayed branch implementation by using a front end track table Mar 16, 2014 Issued
Array ( [id] => 9746827 [patent_doc_number] => 20140282546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHODS, SYSTEMS AND APPARATUS FOR SUPPORTING WIDE AND EFFICIENT FRONT-END OPERATION WITH GUEST-ARCHITECTURE EMULATION' [patent_app_type] => utility [patent_app_number] => 14/216493 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8587 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216493 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216493
Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation Mar 16, 2014 Issued
Array ( [id] => 12173781 [patent_doc_number] => 09891924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method for implementing a reduced size register view data structure in a microprocessor' [patent_app_type] => utility [patent_app_number] => 14/214176 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214176 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/214176
Method for implementing a reduced size register view data structure in a microprocessor Mar 13, 2014 Issued
Array ( [id] => 10376717 [patent_doc_number] => 20150261724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'MASSIVE PARALLEL EXASCALE STORAGE SYSTEM ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/214588 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2681 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/214588
MASSIVE PARALLEL EXASCALE STORAGE SYSTEM ARCHITECTURE Mar 13, 2014 Abandoned
Array ( [id] => 9745692 [patent_doc_number] => 20140281412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR POPULATING AND INSTRUCTION VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS' [patent_app_type] => utility [patent_app_number] => 14/214045 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 9766 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/214045
Method for populating and instruction view data structure by using register template snapshots Mar 13, 2014 Issued
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