Daniel H. Pan

Array ( [id] => 10376717 [patent_doc_number] => 20150261724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'MASSIVE PARALLEL EXASCALE STORAGE SYSTEM ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/214588 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2681 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173781 [patent_doc_number] => 09891924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method for implementing a reduced size register view data structure in a microprocessor' [patent_app_type] => utility [patent_app_number] => 14/214176 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15136887 [patent_doc_number] => 10481911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Synchronization of execution threads on a multi-threaded processor [patent_app_type] => utility [patent_app_number] => 14/177980 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2497 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9513234 [patent_doc_number] => 20140149724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/170397 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 33583 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9903404 [patent_doc_number] => 20150058604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'VERIFYING FORWARDING PATHS IN PIPELINES' [patent_app_type] => utility [patent_app_number] => 14/150974 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6015 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10293089 [patent_doc_number] => 20150178088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'HONORING HARDWARE ENTITLEMENT OF A HARDWARE THREAD' [patent_app_type] => utility [patent_app_number] => 14/134476 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12039436 [patent_doc_number] => 09817670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Framework to provide time bound execution of co-processor commands' [patent_app_type] => utility [patent_app_number] => 14/105349 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6530 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9859847 [patent_doc_number] => 20150039864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SYSTEMS AND METHODS FOR DEFEATING MALWARE WITH RANDOMIZED OPCODE VALUES' [patent_app_type] => utility [patent_app_number] => 14/105788 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9398435 [patent_doc_number] => 20140095841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'PROCESSOR AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/097371 [patent_app_country] => US [patent_app_date] => 2013-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8821 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10215776 [patent_doc_number] => 20150100768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'SCHEDULING PROGRAM INSTRUCTIONS WITH A RUNNER-UP EXECUTION POSITION' [patent_app_type] => utility [patent_app_number] => 14/048141 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3935 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10215766 [patent_doc_number] => 20150100758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'DATA PROCESSOR AND METHOD OF LANE REALIGNMENT' [patent_app_type] => utility [patent_app_number] => 14/045114 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3831 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11390961 [patent_doc_number] => 09552205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions' [patent_app_type] => utility [patent_app_number] => 14/040409 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 25871 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11780874 [patent_doc_number] => 09390058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Dynamic attribute inference' [patent_app_type] => utility [patent_app_number] => 14/034680 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 13746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14034680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9271014 [patent_doc_number] => 20140025932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'PROCESSOR, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/033949 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10781 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9224963 [patent_doc_number] => 20140019738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'MULTICORE PROCESSOR SYSTEM AND BRANCH PREDICTING METHOD' [patent_app_type] => utility [patent_app_number] => 14/029511 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10541 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9912102 [patent_doc_number] => 20150067305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SPECIALIZED MEMORY DISAMBIGUATION MECHANISMS FOR DIFFERENT MEMORY READ ACCESS TYPES' [patent_app_type] => utility [patent_app_number] => 14/015282 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9912186 [patent_doc_number] => 20150067389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'Programmable Substitutions for Microcode' [patent_app_type] => utility [patent_app_number] => 14/014220 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6117 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14014220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9341447 [patent_doc_number] => 20140068231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'CENTRAL PROCESSING UNIT AND ARITHMETIC UNIT' [patent_app_type] => utility [patent_app_number] => 14/013144 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6869 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11578143 [patent_doc_number] => 09633409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'GPU predication' [patent_app_type] => utility [patent_app_number] => 13/975520 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7832 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13975520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9903401 [patent_doc_number] => 20150058601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'VERIFYING FORWARDING PATHS IN PIPELINES' [patent_app_type] => utility [patent_app_number] => 13/970715 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5988 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970715 [rel_patent_id] =>[rel_patent_doc_number] =>)