Search

Daniel H. Pan

Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2315, 2182, 2783, 2899, 2302, 2183
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11465832 [patent_doc_number] => 09582464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Systems, apparatuses, and methods for performing a double blocked sum of absolute differences' [patent_app_type] => utility [patent_app_number] => 13/992229 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 16807 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 645 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992229
Systems, apparatuses, and methods for performing a double blocked sum of absolute differences Dec 22, 2011 Issued
Array ( [id] => 9645026 [patent_doc_number] => 20140223139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE' [patent_app_type] => utility [patent_app_number] => 13/991877 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 21363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991877 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991877
Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate Dec 22, 2011 Issued
Array ( [id] => 11896951 [patent_doc_number] => 09766886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Instruction and logic to provide vector linear interpolation functionality' [patent_app_type] => utility [patent_app_number] => 13/977736 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 16667 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977736 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977736
Instruction and logic to provide vector linear interpolation functionality Dec 15, 2011 Issued
Array ( [id] => 9200361 [patent_doc_number] => 20130339677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'MULTIPLY-AND-ACCUMULATE OPERATION IN AN IMPLANTABLE MICROCONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/001867 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9449 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001867 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001867
MULTIPLY-AND-ACCUMULATE OPERATION IN AN IMPLANTABLE MICROCONTROLLER Apr 13, 2011 Abandoned
Array ( [id] => 11523403 [patent_doc_number] => 09606802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Processor system with predicate register, computer system, method for managing predicates and computer program product' [patent_app_type] => utility [patent_app_number] => 14/006034 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6569 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14006034 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/006034
Processor system with predicate register, computer system, method for managing predicates and computer program product Mar 24, 2011 Issued
Array ( [id] => 11830783 [patent_doc_number] => 09727526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Apparatus and method of vector unit sharing' [patent_app_type] => utility [patent_app_number] => 13/981851 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7071 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13981851 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/981851
Apparatus and method of vector unit sharing Jan 24, 2011 Issued
Array ( [id] => 8120085 [patent_doc_number] => 08161267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 12/956316 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13662 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161267.pdf [firstpage_image] =>[orig_patent_app_number] => 12956316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/956316
Methods and apparatus for scalable array processor interrupt detection and response Nov 29, 2010 Issued
Array ( [id] => 7537634 [patent_doc_number] => 08051277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-01 [patent_title] => 'Programmable arithmetic logic unit cluster' [patent_app_type] => utility [patent_app_number] => 12/903167 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051277.pdf [firstpage_image] =>[orig_patent_app_number] => 12903167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903167
Programmable arithmetic logic unit cluster Oct 11, 2010 Issued
Array ( [id] => 7575420 [patent_doc_number] => 20110271076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Optimizing Task Management' [patent_app_type] => utility [patent_app_number] => 12/769080 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271076.pdf [firstpage_image] =>[orig_patent_app_number] => 12769080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769080
Optimizing task management Apr 27, 2010 Issued
Array ( [id] => 4641939 [patent_doc_number] => 08019973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Information processing apparatus and method of controlling register' [patent_app_type] => utility [patent_app_number] => 12/638764 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10934 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019973.pdf [firstpage_image] =>[orig_patent_app_number] => 12638764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638764
Information processing apparatus and method of controlling register Dec 14, 2009 Issued
Array ( [id] => 4440953 [patent_doc_number] => 07971029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Barrier synchronization method, device, and multi-core processor' [patent_app_type] => utility [patent_app_number] => 12/638746 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4639 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971029.pdf [firstpage_image] =>[orig_patent_app_number] => 12638746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638746
Barrier synchronization method, device, and multi-core processor Dec 14, 2009 Issued
Array ( [id] => 4572755 [patent_doc_number] => 07962732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Instruction processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/654159 [patent_app_country] => US [patent_app_date] => 2009-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12189 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962732.pdf [firstpage_image] =>[orig_patent_app_number] => 12654159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654159
Instruction processing apparatus Dec 10, 2009 Issued
Array ( [id] => 4621631 [patent_doc_number] => 08001362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Processing unit' [patent_app_type] => utility [patent_app_number] => 12/633108 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 9782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001362.pdf [firstpage_image] =>[orig_patent_app_number] => 12633108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/633108
Processing unit Dec 7, 2009 Issued
Array ( [id] => 6510776 [patent_doc_number] => 20100095092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Instruction execution control device and instruction execution control method' [patent_app_type] => utility [patent_app_number] => 12/591994 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8062 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095092.pdf [firstpage_image] =>[orig_patent_app_number] => 12591994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591994
Instruction execution control device and instruction execution control method Dec 6, 2009 Issued
Array ( [id] => 4508202 [patent_doc_number] => 07958338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Instruction execution control device and instruction execution control method' [patent_app_type] => utility [patent_app_number] => 12/591993 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10527 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958338.pdf [firstpage_image] =>[orig_patent_app_number] => 12591993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591993
Instruction execution control device and instruction execution control method Dec 6, 2009 Issued
Array ( [id] => 8087525 [patent_doc_number] => 08151097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Multi-threaded system with branch' [patent_app_type] => utility [patent_app_number] => 12/631143 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7609 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151097.pdf [firstpage_image] =>[orig_patent_app_number] => 12631143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631143
Multi-threaded system with branch Dec 3, 2009 Issued
Array ( [id] => 5486811 [patent_doc_number] => 20090276576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'Methods and Apparatus storing expanded width instructions in a VLIW memory for deferred execution' [patent_app_type] => utility [patent_app_number] => 12/499875 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276576.pdf [firstpage_image] =>[orig_patent_app_number] => 12499875 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499875
Methods and apparatus storing expanded width instructions in a VLIW memory deferred execution Jul 8, 2009 Issued
Array ( [id] => 7746349 [patent_doc_number] => 08108661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Data processing apparatus and method of controlling the data processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/385265 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108661.pdf [firstpage_image] =>[orig_patent_app_number] => 12385265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385265
Data processing apparatus and method of controlling the data processing apparatus Apr 1, 2009 Issued
Array ( [id] => 6363887 [patent_doc_number] => 20100250905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'System and Method of Routing Instructions' [patent_app_type] => utility [patent_app_number] => 12/412889 [patent_app_country] => US [patent_app_date] => 2009-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4462 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250905.pdf [firstpage_image] =>[orig_patent_app_number] => 12412889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/412889
Routing instructions in a processor Mar 26, 2009 Issued
Array ( [id] => 6363857 [patent_doc_number] => 20100250901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Selecting Fixed-Point Instructions to Issue on Load-Store Unit' [patent_app_type] => utility [patent_app_number] => 12/410073 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250901.pdf [firstpage_image] =>[orig_patent_app_number] => 12410073 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/410073
Selecting fixed-point instructions to issue on load-store unit Mar 23, 2009 Issued
Menu